Recently, learned image compression (LIC) has shown a superior ability in the compression ratio as well as the quality of the reconstructed image. By adopting the framework of variational autoencoder, LIC  can outperform the intra prediction of the latest traditional coding standard VVC. To accelerate the coding speed, most LIC frameworks are operated on GPU with the floating-point arithmetic. However, the mismatch of floating-point calculation results on various hardware platforms will cause the decoding error if encoding and decoding are performed on different platforms. Therefore, LIC with a fixed-point arithmetic [2-3] is highly required. This paper gives an FPGA design for a LIC with 8-bit fixed-point quantization. Different from existing FPGA accelerators [4-6], we propose a fine-grained pipeline architecture to realize high DSP efficiency. Cascading DSP and the deconvolution with zero skipping are also developed to enhance the hardware performance.