Fabrication of nano-sized single-walled carbon nanotube vias for electronic device applications

T. Iwasaki*, R. Morikane, G. Zhong, T. Edura, K. Tsutsui, Y. Wada, H. Kawarada

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Vertically aligned single-walled carbon nanotubes (SWNTs) were synthesized at a low temperature of 600°C by radical chemical vapor deposition (CVD). For applying this technique to electronic devices, we synthesized SWNTs in nano-sized SiO2 holes to fabricate SWNT-vias, which is expected to be used for multi-layer interconnects and vertically aligned field effect transistors (FET). SWNTs were grown in holes with various sizes and shapes patterned by electron beam lithography. We also show the concept of large area deposition of vertically aligned SWNTs by improved radical CVD system.

Original languageEnglish
Title of host publication2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
Pages94-97
Number of pages4
Publication statusPublished - 2006
Event2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings - Boston, MA, United States
Duration: 2006 May 72006 May 11

Publication series

Name2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
Volume1

Conference

Conference2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
Country/TerritoryUnited States
CityBoston, MA
Period06/5/706/5/11

Keywords

  • Nano-sized via
  • Radical chemical vapor deposition
  • Single-walled carbon nanotubes
  • Vertically aligned

ASJC Scopus subject areas

  • General Engineering

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