Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE)

Meishoku Masahara; Takashi Matsukawa; Kenichi Ishii; Yongxun Liu; Masayoshi Nagao; Hisao Tanoue; Takashi Tanii; Iwao Ohdomari; Seigo Kanemaru; Eiichi Suzuki

doi:10.1143/jjap.42.1916

Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE)

Meishoku Masahara^*, Takashi Matsukawa, Kenichi Ishii, Yongxun Liu, Masayoshi Nagao, Hisao Tanoue, Takashi Tanii, Iwao Ohdomari, Seigo Kanemaru, Eiichi Suzuki

^*Corresponding author for this work

School of Fundamental Science and Engineering

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

It was found that the etch rate of Si in tetramethylammonium hydroxide (TMAH) solution is significantly retarded by introducing ion implantation damage. By utilizing this new phenomenon, i.e., ion-bombardment-retarded etching (IBRE) of Si, a novel process to fabricate an ultrathin Si channel wall for the vertical double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) was developed. We succeeded in fabricating a vertical Si wall with thickness of 16 nm on bulk Si substrate with no introduction of dry etching damage. The effectiveness of thinning the Si channel wall to the characteristics of a vertical DG MOSFET was examined by means of simulations.

Original language	English
Pages (from-to)	1916-1918
Number of pages	3
Journal	Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume	42
Issue number	4 B
DOIs	https://doi.org/10.1143/jjap.42.1916
Publication status	Published - 2003 Apr

Keywords

Ion implantation
Ion-bombardment-retarded etching of Si
TMAH
Ultrathin Si wall
Vertical double-gate MOSFET
Wet etching

ASJC Scopus subject areas

Engineering(all)
Physics and Astronomy(all)

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10.1143/jjap.42.1916

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Masahara, M., Matsukawa, T., Ishii, K., Liu, Y., Nagao, M., Tanoue, H., Tanii, T., Ohdomari, I., Kanemaru, S., & Suzuki, E. (2003). Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE). Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 42(4 B), 1916-1918. https://doi.org/10.1143/jjap.42.1916

Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE). / Masahara, Meishoku; Matsukawa, Takashi; Ishii, Kenichi et al.
In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol. 42, No. 4 B, 04.2003, p. 1916-1918.

Research output: Contribution to journal › Article › peer-review

Masahara, M, Matsukawa, T, Ishii, K, Liu, Y, Nagao, M, Tanoue, H, Tanii, T, Ohdomari, I, Kanemaru, S & Suzuki, E 2003, 'Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE)', Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, vol. 42, no. 4 B, pp. 1916-1918. https://doi.org/10.1143/jjap.42.1916

Masahara M, Matsukawa T, Ishii K, Liu Y, Nagao M, Tanoue H et al. Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE). Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 2003 Apr;42(4 B):1916-1918. doi: 10.1143/jjap.42.1916

Masahara, Meishoku ; Matsukawa, Takashi ; Ishii, Kenichi et al. / Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE). In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 2003 ; Vol. 42, No. 4 B. pp. 1916-1918.

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abstract = "It was found that the etch rate of Si in tetramethylammonium hydroxide (TMAH) solution is significantly retarded by introducing ion implantation damage. By utilizing this new phenomenon, i.e., ion-bombardment-retarded etching (IBRE) of Si, a novel process to fabricate an ultrathin Si channel wall for the vertical double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) was developed. We succeeded in fabricating a vertical Si wall with thickness of 16 nm on bulk Si substrate with no introduction of dry etching damage. The effectiveness of thinning the Si channel wall to the characteristics of a vertical DG MOSFET was examined by means of simulations.",

keywords = "Ion implantation, Ion-bombardment-retarded etching of Si, TMAH, Ultrathin Si wall, Vertical double-gate MOSFET, Wet etching",

author = "Meishoku Masahara and Takashi Matsukawa and Kenichi Ishii and Yongxun Liu and Masayoshi Nagao and Hisao Tanoue and Takashi Tanii and Iwao Ohdomari and Seigo Kanemaru and Eiichi Suzuki",

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AU - Masahara, Meishoku

AU - Matsukawa, Takashi

AU - Ishii, Kenichi

AU - Liu, Yongxun

AU - Nagao, Masayoshi

AU - Tanoue, Hisao

AU - Tanii, Takashi

AU - Ohdomari, Iwao

AU - Kanemaru, Seigo

AU - Suzuki, Eiichi

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AB - It was found that the etch rate of Si in tetramethylammonium hydroxide (TMAH) solution is significantly retarded by introducing ion implantation damage. By utilizing this new phenomenon, i.e., ion-bombardment-retarded etching (IBRE) of Si, a novel process to fabricate an ultrathin Si channel wall for the vertical double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) was developed. We succeeded in fabricating a vertical Si wall with thickness of 16 nm on bulk Si substrate with no introduction of dry etching damage. The effectiveness of thinning the Si channel wall to the characteristics of a vertical DG MOSFET was examined by means of simulations.

KW - Ion implantation

KW - Ion-bombardment-retarded etching of Si

KW - TMAH

KW - Ultrathin Si wall

KW - Vertical double-gate MOSFET

KW - Wet etching

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Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE)

Abstract

Keywords

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