Fast custom instruction identification algorithm based on basic convex pattern model for supporting asip automated design

Kang Zhao; Jinian Bian; Sheqin Dong; Yang Song; Satoshi Goto

doi:10.1093/ietfec/e91-a.6.1478

Fast custom instruction identification algorithm based on basic convex pattern model for supporting asip automated design

Kang Zhao^*, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

In this paper, a generalized Montgomery multiplication algorithm in GF(2^m) using the Toeplitz matrix-vector representation is presented. The hardware architectures derived from this algorithm provide low-complexity bit-parallel systolic multipliers with trinomials and pen-tanomials. The results reveal that our proposed multipliers reduce the space complexity of approximately 15% compared with an existing systolic Montgomery multiplier for trinomials. Moreover, the proposed architectures have the features of regularity, modularity, and local interconnection. Accordingly, they are well suited to VLSI implementation.

Original language	English
Pages (from-to)	1478-1487
Number of pages	10
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E91-A
Issue number	6
DOIs	https://doi.org/10.1093/ietfec/e91-a.6.1478
Publication status	Published - 2008

Keywords

Application specific instruction-set processor (ASIP)
Basic convex pattern (BCP)
Custom instruction identification
System-on-a-chip (SoC)

ASJC Scopus subject areas

Electrical and Electronic Engineering
Computer Graphics and Computer-Aided Design
Applied Mathematics
Signal Processing

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10.1093/ietfec/e91-a.6.1478

Cite this

Fast custom instruction identification algorithm based on basic convex pattern model for supporting asip automated design. / Zhao, Kang; Bian, Jinian; Dong, Sheqin et al.
In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E91-A, No. 6, 2008, p. 1478-1487.

Research output: Contribution to journal › Article › peer-review

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AU - Goto, Satoshi

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AB - In this paper, a generalized Montgomery multiplication algorithm in GF(2m) using the Toeplitz matrix-vector representation is presented. The hardware architectures derived from this algorithm provide low-complexity bit-parallel systolic multipliers with trinomials and pen-tanomials. The results reveal that our proposed multipliers reduce the space complexity of approximately 15% compared with an existing systolic Montgomery multiplier for trinomials. Moreover, the proposed architectures have the features of regularity, modularity, and local interconnection. Accordingly, they are well suited to VLSI implementation.

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Fast custom instruction identification algorithm based on basic convex pattern model for supporting asip automated design

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Keywords

ASJC Scopus subject areas

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