Fast methods to estimate clock jitter due to power supply noise

Koutaro Hachiya*, Takayuki Ohshima, Hidenari Nakashima, Masaaki Soda, Satoshi Goto

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


In this paper, we propose two methods to estimate clock jitter caused by power supply noise in a LSI (Large-Scale Integrated circuit). One of the methods enables estimation of clock jitter at the initial design stage before floor-planning. The other method reduces simulation time of clock distribution network to analyze clock jitter at the design verification stage after place-and-route of the chip. For an example design, the relative difference between clock jitter estimated at the initial design stage and that of the design verification stage is 23. The example result also shows that the proposed method for the verification stage is about 24 times faster than the conventional one to analyze clock jitter.

Original languageEnglish
Pages (from-to)741-747
Number of pages7
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number4
Publication statusPublished - 2007 Apr


  • Clock distribution network
  • Clock jitter
  • Power distribution network
  • Power supply noise

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Information Systems


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