Fast scheduling and allocation algorithms for entropy CODEC

Katsuharu Suzuki*, Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


Entropy coding/decoding are implemented on FPGAs as a fast and flexible system in which high-level synthesis technologies are key issues. In this paper, we propose scheduling and allocation algorithms for behavioral descriptions of entropy CODEC. The scheduling algorithm employs a control-flow graph as input and finds a solution with minimal hardware cost and execution time by merging nodes in the control-flow graph. The allocation algorithm assigns operations to operators with various bit lengths. As a result, register-transfer level descriptions are efficiently obtained from behavioral descriptions of entropy CODEC with complicated control flow and variable bit lengths. Experimental results demonstrate that our algorithms synthesize the same circuits as manually designed within one second.

Original languageEnglish
Pages (from-to)982-992
Number of pages11
JournalIEICE Transactions on Information and Systems
Issue number10
Publication statusPublished - 1997 Jan 1


  • Allocation
  • Control-flow graph
  • Entropy CODEC
  • Scheduling

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence


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