FBC (Floating Body Cell) for Embedded DRAM on SOI

Kazumi Inoh*, Tomoaki Shino, Hiroaki Yamada, Hiroomi Nakajima, Yoshihiro Minami, Takashi Yamada, Takashi Ohsawa, Tomoki Higashi, Katsuyuki Fujita, Tamio Ikehashi, Takeshi Kajiyama, Yoshiaki Fukuzumi, Takeshi Hamamoto, Hidemi Ishiuchi

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

35 Citations (Scopus)


The memory cell characteristics of the FBC (Floating Body Cell) have been experimentally verified by 0.17μm cell array for the first time. The FBC is a one-transistor gain cell, which is a suitable structure for the future embedded DRAM on SOI wafer. The memory cell layout and the process integration have been designed from the viewpoint of the logic process compatibility without sacrificing the data retention characteristics. The salicide process with the poly-Si plug is implemented into the process integration. The most important device characteristics for realizing the FBC is the threshold voltage difference (Δ Vth) of the cell transistor between "1" state and "0" state. The key device parameters in order to enlarge the Δ Vth are experimentally clarified. A Δ Vth of 0.4V has been obtained, which leads to 99.77% function bit yield of 96Kbit ADM (Array Diagnostic Monitor). The retention time of 5sec has been realized at the room temperature.

Original languageEnglish
Pages (from-to)63-64
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
Publication statusPublished - 2003
Externally publishedYes
Event2003 Symposium on VLSI Technology - Kyoto, Japan
Duration: 2003 Jun 102003 Jun 12

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'FBC (Floating Body Cell) for Embedded DRAM on SOI'. Together they form a unique fingerprint.

Cite this