Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

Shigenobu Maeda*, Yoshiki Wada, Kazuya Yamamoto, Hiroshi Komurasaki, Takuji Matsumoto, Yuuichi Hirano, Toshiaki Iwamatsu, Yasuo Yamaguchi, Takashi Ipposhi, Kimio Ueda, Koichiro Mashiko, Shigeto Maegawa, Masahide Inuishi

*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

17 Citations (Scopus)

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Engineering & Materials Science

Chemical Compounds