Finite input-memory automaton based checker synthesis of systemverilog assertions for FPGA prototyping

Chengjie Zang*, Shinji Kimura

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


Checker synthesis for assertion based verification becomes popular because of the recent progress on the FPGA prototyping environment. In the paper, we propose a checker synthesis method based on the finite input-memory automaton suitable for embedded RAMmodules in FPGA. There are more than 1Mbit memories in medium size FPGA's and such embedded memory cells have the capability to be used as the shift registers. The main idea is to construct a checker circuit using the finite inputmemory automata and implement shift register chain by logic elements or embedded RAM modules. When using RAM module, the method does not consume any logic element for storing the value. Note that the shift register chain of input memory can be shared with different assertions and we can reduce the hardware resource significantly. We have checked the effectiveness of the proposed method using several assertions.

Original languageEnglish
Pages (from-to)1454-1463
Number of pages10
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number6
Publication statusPublished - 2009


  • Assertion checker
  • Finite inputmemory automaton
  • SystemVerilog Assertion

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics


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