Floorplanning and topology generation for application-specific network-on-chip

Bei Yu; Sheqin Dong; Song Chen; Satoshino Goto

doi:10.1109/ASPDAC.2010.5419825

Floorplanning and topology generation for application-specific network-on-chip

Bei Yu^*, Sheqin Dong, Song Chen, Satoshino Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

39 Citations (Scopus)

Abstract

Network-on-Chip(NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation problem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, we allocate paths to minimize power consumption. The experimental results show our algorithm is effective for power saving.

Original language	English
Title of host publication	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages	535-540
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2010.5419825
Publication status	Published - 2010
Event	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei Duration: 2010 Jan 18 → 2010 Jan 21

Other

Other	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
City	Taipei
Period	10/1/18 → 10/1/21

ASJC Scopus subject areas

Electrical and Electronic Engineering
Computer Science Applications
Computer Graphics and Computer-Aided Design

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10.1109/ASPDAC.2010.5419825

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title = "Floorplanning and topology generation for application-specific network-on-chip",

abstract = "Network-on-Chip(NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation problem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, we allocate paths to minimize power consumption. The experimental results show our algorithm is effective for power saving.",

author = "Bei Yu and Sheqin Dong and Song Chen and Satoshino Goto",

year = "2010",

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language = "English",

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pages = "535--540",

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note = "2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 ; Conference date: 18-01-2010 Through 21-01-2010",

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T1 - Floorplanning and topology generation for application-specific network-on-chip

AU - Yu, Bei

AU - Dong, Sheqin

AU - Chen, Song

AU - Goto, Satoshino

PY - 2010

Y1 - 2010

N2 - Network-on-Chip(NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation problem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, we allocate paths to minimize power consumption. The experimental results show our algorithm is effective for power saving.

AB - Network-on-Chip(NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation problem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, we allocate paths to minimize power consumption. The experimental results show our algorithm is effective for power saving.

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U2 - 10.1109/ASPDAC.2010.5419825

DO - 10.1109/ASPDAC.2010.5419825

M3 - Conference contribution

AN - SCOPUS:77951241271

SN - 9781424457656

SP - 535

EP - 540

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

T2 - 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010

Y2 - 18 January 2010 through 21 January 2010

ER -

Floorplanning and topology generation for application-specific network-on-chip

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