Folding of logic functions and its application to look up table compaction

Shinji Kimura*, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

11 Citations (Scopus)


The paper describes the folding method of logic functions to reduce the size of memories for keeping the functions. The folding is based on the relation of fractions of logic functions. We show that the fractions of the full adder function have the bit-wise NOT relation and the bit-wise OR relation, and that the memory size becomes half (8-bit). We propose a new 3-1 LUT with the folding mechanisms which can implement a full adder with one LUT. A fast carry propagation line is introduced for a multi-bit addition. The folding and fast carry propagation mechanisms are shown to be useful to implement other multi-bit operations and general 4 input functions without extra hardware resources. The paper shows the reduction of the area consumption when using our LUTs compared to the case using 4-1 LUTs on several benchmark circuits.

Original languageEnglish
Pages (from-to)694-697
Number of pages4
JournalIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Publication statusPublished - 2002
EventIEEE/ACM International Conference on Computer Aided Design (ICCAD) - San Jose, CA, United States
Duration: 2002 Nov 102002 Nov 14

ASJC Scopus subject areas

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design


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