Formula-based method for capacitance extraction of interconnects with dummy fills

Atsushi Kurokawa*, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    1 Citation (Scopus)


    In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects with dummy fills for VLSI designs. The whole flow is as follows: 1) in each process, obtain capacitances per unit length using a 3-D field solver and then create formulas, and 2) in the actual design phase, execute a well-known 2.5-D capacitance extraction. Our results indicated that accuracies of the proposed formulas were almost within 3% error. The proposed formula-based method can extract interconnect capacitances with high accuracy for VLSI circuits. Moreover, we present formulas to evaluate the effect of dummy fills on interconnect capacitances. These can be useful for determining design guidelines, such as metal density before the actual design, and for analyzing the effect of each structural parameter during the design phase.

    Original languageEnglish
    Pages (from-to)847-855
    Number of pages9
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    Issue number4
    Publication statusPublished - 2006 Apr


    • Capacitance extraction
    • Capacitance formula
    • Dummy fill
    • Interconnect

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems


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