Framework for parallel prefix adder synthesis considering switching activities

Taeko Matsunaga*, Shinji Kimura, Yusuke Matsunaga

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


This paper addresses parallel prefix adder synthesis which aims at minimizing the total switching activity under bitwise timing constraints. This problem is treated as synthesis of prefix graphs which represent global structures of parallel prefix adders at technology-independent level. An approach for timing-driven area minimization of prefix graphs has been already proposed which first finds the exact minimum solution on a specific subset of prefix graphs by dynamic programming, then restructures the result for further reduction by removing restrictions on the subset. In this paper, a switching cost of each node of a prefix graph is defined, and an approach to minimize the total switching cost is presented where our area minimization algorithm is extended to be able to calculate the switching cost using Ordered Binary-Decision Diagrams (OBDDs). Furthermore, a heuristic is integrated which estimates the effect of the restructuring phase in the dynamic programming phase, to improve the robustness of our algorithm under severe timing constraints. Through a series of experiments, the proposed approach is shown to be effective especially when timing constraints are not tight and/or there are comparably a large number of nodes with very low switching costs.

Original languageEnglish
Pages (from-to)212-221
Number of pages10
JournalIPSJ Transactions on System LSI Design Methodology
Publication statusPublished - 2009

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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