Hardware architecture design of CABAC Codec for H.264/AVC

Lingfeng Li; Yang Song; Takeshi Ikenaga; Satoshi Goto

doi:10.1109/VDAT.2007.373257

Hardware architecture design of CABAC Codec for H.264/AVC

Lingfeng Li^*, Yang Song, Takeshi Ikenaga, Satoshi Goto

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

This paper presents a hardware architecture for Context-Based Adaptive Binary Arithmetic Coding (CABAC) codec in H.264/AVC main profile. The similarities between encoding algorithm and decoding algorithm are explored to fulfill hardware reuse. Meanwhile, dynamic pipeline scheme is adopted, to speedup the throughput. The characteristics of CABAC algorithm are utilized to reduce pipeline latency. Proposed codec design is implemented under TSMC 0.18 μm technology. Results show that the equivalent gate counts is 33.2k when the maximum frequency is 230MHz. It is estimated that the proposed CABAC, codec can process the input binary symbol at 135Mb/s for encoding and 90Mb/s for decoding.

Original language	English
Title of host publication	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOIs	https://doi.org/10.1109/VDAT.2007.373257
Publication status	Published - 2007 Sept 28
Event	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu, Taiwan, Province of China Duration: 2007 Apr 25 → 2007 Apr 27

Publication series

Name	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

Conference

Conference	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	07/4/25 → 07/4/27

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/VDAT.2007.373257

Cite this

Li, L., Song, Y., Ikenaga, T., & Goto, S. (2007). Hardware architecture design of CABAC Codec for H.264/AVC. In 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers Article 4239449 (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2007.373257

Hardware architecture design of CABAC Codec for H.264/AVC. / Li, Lingfeng; Song, Yang; Ikenaga, Takeshi et al.
2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 2007. 4239449 (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Li, L, Song, Y, Ikenaga, T & Goto, S 2007, Hardware architecture design of CABAC Codec for H.264/AVC. in 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers., 4239449, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007, Hsinchu, Taiwan, Province of China, 07/4/25. https://doi.org/10.1109/VDAT.2007.373257

Li L, Song Y, Ikenaga T, Goto S. Hardware architecture design of CABAC Codec for H.264/AVC. In 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 2007. 4239449. (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers). doi: 10.1109/VDAT.2007.373257

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Hardware architecture design of CABAC Codec for H.264/AVC

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