Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC

Zhenyu Liu; Yiqing Huang; Yang Song; Satoshi Goto; Takeshi Ikenaga

doi:10.1145/1228784.1228826

Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC

Zhenyu Liu^*, Yiqing Huang, Yang Song, Satoshi Goto, Takeshi Ikenaga

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

19 Citations (Scopus)

Abstract

One hardware efficient and high speed architecture for variableblock size motion estimation in H.264 is presented in this paper. Through compressing the propagated data and optimizing theprocessing element and adder tree circuits in pipeline, this architecture gets more hardware efficient datapath logic. Compared with the original Propagate Partial SAD structure, 12.1% hardware cost can be saved. With TSMC 0.18m CMOS 1P6M standard celllibrary, the maximum clock speed of this design is 227MHz in worstwork conditions (1.62V, 125°C). With the 48x32 search range, the maximum throughput of our design is 147786 MB/S, which can be used in the real-time encoding of VGA resolution frame with 4 reference frames at 30Hz.

Original language	English
Title of host publication	GLSVLSI'07
Subtitle of host publication	Proceedings of the 2007 ACM Great Lakes Symposium on VLSI
Pages	160-163
Number of pages	4
DOIs	https://doi.org/10.1145/1228784.1228826
Publication status	Published - 2007
Event	17th Great Lakes Symposium on VLSI, GLSVLSI'07 - Stresa-Lago Maggiore, Italy Duration: 2007 Mar 11 → 2007 Mar 13

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference	17th Great Lakes Symposium on VLSI, GLSVLSI'07
Country/Territory	Italy
City	Stresa-Lago Maggiore
Period	07/3/11 → 07/3/13

Keywords

H.264
VLSI
Variable block size motion estimation

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1145/1228784.1228826

Cite this

Liu, Z., Huang, Y., Song, Y., Goto, S., & Ikenaga, T. (2007). Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC. In GLSVLSI'07: Proceedings of the 2007 ACM Great Lakes Symposium on VLSI (pp. 160-163). Article 1228826 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI). https://doi.org/10.1145/1228784.1228826

Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC. / Liu, Zhenyu; Huang, Yiqing; Song, Yang et al.
GLSVLSI'07: Proceedings of the 2007 ACM Great Lakes Symposium on VLSI. 2007. p. 160-163 1228826 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Liu, Z, Huang, Y, Song, Y, Goto, S & Ikenaga, T 2007, Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC. in GLSVLSI'07: Proceedings of the 2007 ACM Great Lakes Symposium on VLSI., 1228826, Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, pp. 160-163, 17th Great Lakes Symposium on VLSI, GLSVLSI'07, Stresa-Lago Maggiore, Italy, 07/3/11. https://doi.org/10.1145/1228784.1228826

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Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC

Abstract

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Keywords

ASJC Scopus subject areas

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