Hardware synthesis from C programs with estimation of bit length of variables

Osamu Ogawa*, Kazuyoshi Takagi, Yasufumi Itoh, Shinji Kimura, Katsumasa Watanabe

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)


In the hardware synthesis methods with high level languages such as C language optimization quality of the compilers has a great influence on the area and speed of the synthesized circuits. Among hardware-oriented optimization methods required in such compilers minimization of the bit length of the data-paths is one of the most important issues. In this paper we propose an estimation algorithm of the necessary bit length of variables for this aim. The algorithm analyzes the control/dataflow graph translated from C programs and decides the bit length of each variable. On several experiments the bit length of variables can be reduced by half with respect to the declared length. This method is effective not only for reducing the circuit area but also for reducing the delay of the operation units such as adders.

Original languageEnglish
Pages (from-to)2338-2346
Number of pages9
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number11
Publication statusPublished - 1999 Jan 1
Externally publishedYes


  • C language
  • Compiler
  • Hardware/software codesign
  • High-level synthesis
  • VHDL

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics


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