Heterogeneous multiprocessor on a chip which enables 54x AAC-LC stereo encoding

Masaki Ito*, Takashi Todaka, Takanobu Tsunoda, Hiroshi Tanaka, Tomoyuki Kodama, Hiroaki Shikano, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)


A heterogeneous multiprocessor on a chip has been designed and implemented. It consists of 2 CPUs and 2 DRPs (Dynamic Reconfigurable Processors). The design of DRP was intended to achieve high-performance in a small area to be integrated on a SoC for embedded systems. Memory architecture of CPUs and DRPs were unified to improve programming and compiling efficiency. 54x AAC-LC stereo encoding has been enabled with 2 DRPs at 300MHz and 2 CPUs at 600MHz.

Original languageEnglish
Title of host publication2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Number of pages2
Publication statusPublished - 2007 Dec 1
Event2007 Symposium on VLSI Circuits, VLSIC - Kyoto, Japan
Duration: 2007 Jun 142007 Jun 16

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers


Other2007 Symposium on VLSI Circuits, VLSIC


  • Dynamic reconfigurable processor
  • Embedded system and AAC
  • Multiprocessor
  • SoC

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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