High performance and low latency mapping for neural network into network on chip architecture

Yiping Dong; Yang Wang; Zhen Lin; Takahiro Watanabe

doi:10.1109/ASICON.2009.5351550

High performance and low latency mapping for neural network into network on chip architecture

Yiping Dong^*, Yang Wang, Zhen Lin, Takahiro Watanabe

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

Various hardware implementations of neural networks have been studied well in recent years. We have already proposed a hardware implementation method for neural network with a Network on Chip (NoC) architecture. A mapping of a neural network on NoC should be tuned to achieve high performance whenever neural network application is changed, so that different mapping methods are needed every time and tedious or burdensome works are required In this paper, we propose a general mapping strategy based on three rules. The mapping method with this strategy can implement different neural networks applications with NoC architecture. The simulation results show that the proposed method makes the system low latency and high performance.

Original language	English
Title of host publication	ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
Pages	891-894
Number of pages	4
DOIs	https://doi.org/10.1109/ASICON.2009.5351550
Publication status	Published - 2009
Event	2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, China Duration: 2009 Oct 20 → 2009 Oct 23

Publication series

Name	ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

Other

Other	2009 8th IEEE International Conference on ASIC, ASICON 2009
Country/Territory	China
City	Changsha
Period	09/10/20 → 09/10/23

Keywords

Artificial neural network (ANN)
Hardware implementation
Mapping method
Network on Chip (NoC)
NoC architecture

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASICON.2009.5351550

Cite this

Dong, Y., Wang, Y., Lin, Z., & Watanabe, T. (2009). High performance and low latency mapping for neural network into network on chip architecture. In ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC (pp. 891-894). Article 5351550 (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC). https://doi.org/10.1109/ASICON.2009.5351550

High performance and low latency mapping for neural network into network on chip architecture. / Dong, Yiping; Wang, Yang; Lin, Zhen et al.
ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC. 2009. p. 891-894 5351550 (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Dong, Y, Wang, Y, Lin, Z & Watanabe, T 2009, High performance and low latency mapping for neural network into network on chip architecture. in ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC., 5351550, ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC, pp. 891-894, 2009 8th IEEE International Conference on ASIC, ASICON 2009, Changsha, China, 09/10/20. https://doi.org/10.1109/ASICON.2009.5351550

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title = "High performance and low latency mapping for neural network into network on chip architecture",

abstract = "Various hardware implementations of neural networks have been studied well in recent years. We have already proposed a hardware implementation method for neural network with a Network on Chip (NoC) architecture. A mapping of a neural network on NoC should be tuned to achieve high performance whenever neural network application is changed, so that different mapping methods are needed every time and tedious or burdensome works are required In this paper, we propose a general mapping strategy based on three rules. The mapping method with this strategy can implement different neural networks applications with NoC architecture. The simulation results show that the proposed method makes the system low latency and high performance.",

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AB - Various hardware implementations of neural networks have been studied well in recent years. We have already proposed a hardware implementation method for neural network with a Network on Chip (NoC) architecture. A mapping of a neural network on NoC should be tuned to achieve high performance whenever neural network application is changed, so that different mapping methods are needed every time and tedious or burdensome works are required In this paper, we propose a general mapping strategy based on three rules. The mapping method with this strategy can implement different neural networks applications with NoC architecture. The simulation results show that the proposed method makes the system low latency and high performance.

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KW - NoC architecture

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High performance and low latency mapping for neural network into network on chip architecture

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Keywords

ASJC Scopus subject areas

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