TY - GEN
T1 - High performance autoassociative neural network using network on chip
AU - Dong, Yiping
AU - Lin, Zhen
AU - Watanabe, Takahiro
PY - 2009/12/1
Y1 - 2009/12/1
N2 - In this paper, an Artificial Autoassociative Neural Network (AANN) is implemented by Network on Chip (NoC) architecture to solve communication and performance problem. This proposed NoC based system can map four neurons in one PE and the whole system consists of PEs each of which connects with a router. This system is reconfigurable and extendable so that it can easily suit for different applications. Simulation results show that the proposed implementation method can reduce communication load and total computation time.
AB - In this paper, an Artificial Autoassociative Neural Network (AANN) is implemented by Network on Chip (NoC) architecture to solve communication and performance problem. This proposed NoC based system can map four neurons in one PE and the whole system consists of PEs each of which connects with a router. This system is reconfigurable and extendable so that it can easily suit for different applications. Simulation results show that the proposed implementation method can reduce communication load and total computation time.
KW - Artificial Autoassociative Neural Network (AANN)
KW - Communication load
KW - Network on Chip (NoC)
KW - NoC implementation method
UR - http://www.scopus.com/inward/record.url?scp=77952777036&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77952777036&partnerID=8YFLogxK
U2 - 10.1109/ICISE.2009.633
DO - 10.1109/ICISE.2009.633
M3 - Conference contribution
AN - SCOPUS:77952777036
SN - 9780769538877
T3 - 2009 1st International Conference on Information Science and Engineering, ICISE 2009
SP - 4015
EP - 4018
BT - 2009 1st International Conference on Information Science and Engineering, ICISE 2009
T2 - 1st International Conference on Information Science and Engineering, ICISE2009
Y2 - 26 December 2009 through 28 December 2009
ER -