HIGH PERFORMANCE LSI DIGITAL SIGNAL PROCESSOR FOR COMMUNICATION.

Yukou Mochida; Kazuo Murano; Toshitaka Tsuda; Hirohisa Gambe; Shigeru Fujii

HIGH PERFORMANCE LSI DIGITAL SIGNAL PROCESSOR FOR COMMUNICATION.

Yukou Mochida^*, Kazuo Murano, Toshitaka Tsuda, Hirohisa Gambe, Shigeru Fujii

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

This paper describes a newly developed CMOS LSI DSP (FDSP3). It has a powerful multiplier, which operates at a rate of 10 M-operations/s, almost twice as fast as the fastest existing LSI DSP's. Some key techniques to attain these high performance characteristics of the DSP are described. Suitable memory capacities of the RAM and ROM were analyzed as a function of the operational capability of the DSP. These were reflected in the design of the FDSP3. To assist in the development of the program, support tools have been developed. A Pascal based cross compiler and an on-line debugging tool are described.

Original language	English
Pages (from-to)	347-356
Number of pages	10
Journal	IEEE Journal on Selected Areas in Communications
Volume	SAC-3
Issue number	2
Publication status	Published - 1985 Mar

ASJC Scopus subject areas

Computer Networks and Communications
Electrical and Electronic Engineering

Cite this

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abstract = "This paper describes a newly developed CMOS LSI DSP (FDSP3). It has a powerful multiplier, which operates at a rate of 10 M-operations/s, almost twice as fast as the fastest existing LSI DSP's. Some key techniques to attain these high performance characteristics of the DSP are described. Suitable memory capacities of the RAM and ROM were analyzed as a function of the operational capability of the DSP. These were reflected in the design of the FDSP3. To assist in the development of the program, support tools have been developed. A Pascal based cross compiler and an on-line debugging tool are described.",

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AU - Mochida, Yukou

AU - Murano, Kazuo

AU - Tsuda, Toshitaka

AU - Gambe, Hirohisa

AU - Fujii, Shigeru

PY - 1985/3

Y1 - 1985/3

N2 - This paper describes a newly developed CMOS LSI DSP (FDSP3). It has a powerful multiplier, which operates at a rate of 10 M-operations/s, almost twice as fast as the fastest existing LSI DSP's. Some key techniques to attain these high performance characteristics of the DSP are described. Suitable memory capacities of the RAM and ROM were analyzed as a function of the operational capability of the DSP. These were reflected in the design of the FDSP3. To assist in the development of the program, support tools have been developed. A Pascal based cross compiler and an on-line debugging tool are described.

AB - This paper describes a newly developed CMOS LSI DSP (FDSP3). It has a powerful multiplier, which operates at a rate of 10 M-operations/s, almost twice as fast as the fastest existing LSI DSP's. Some key techniques to attain these high performance characteristics of the DSP are described. Suitable memory capacities of the RAM and ROM were analyzed as a function of the operational capability of the DSP. These were reflected in the design of the FDSP3. To assist in the development of the program, support tools have been developed. A Pascal based cross compiler and an on-line debugging tool are described.

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ER -

HIGH PERFORMANCE LSI DIGITAL SIGNAL PROCESSOR FOR COMMUNICATION.

Abstract

ASJC Scopus subject areas

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