High performance NoC architecture for two hidden layers BP neural network

Yiping Dong; Takahiro Watanabe

doi:10.1109/SOCDC.2008.4815624

High performance NoC architecture for two hidden layers BP neural network

Yiping Dong^*, Takahiro Watanabe

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Artificial Neural Networks (ANNs)are widely used in applications of an intelligent system such as pattern recognition, fuzzy system, optimization and control. We have already proposed a novel NoC architecture for different kinds of BPANNs [1][2] and it was shown that the architecture is a promising hardware implementation for Neural Network. However, some problems to be solved are still remained. One of them is performance. In this paper, we propose another NoC architecture, network topology and routing strategy for higher performance. Experimental results by NoC simulator show that this new architecture and routing strategy reduce the communication load, reduce both latency by 7.7% and dynamic power consumption by 10.3% and also improve throughput by 8.1%, all compared with the previous one.

Original language	English
Title of host publication	2008 International SoC Design Conference, ISOCC 2008
Pages	I269-I272
DOIs	https://doi.org/10.1109/SOCDC.2008.4815624
Publication status	Published - 2008 Dec 1
Event	2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of Duration: 2008 Nov 24 → 2008 Nov 25

Publication series

Name	2008 International SoC Design Conference, ISOCC 2008
Volume	1

Conference

Conference	2008 International SoC Design Conference, ISOCC 2008
Country/Territory	Korea, Republic of
City	Busan
Period	08/11/24 → 08/11/25

Keywords

Architecture
Network on Chip
Neural Network

ASJC Scopus subject areas

Hardware and Architecture
Software

Access to Document

10.1109/SOCDC.2008.4815624

Cite this

Dong, Y & Watanabe, T 2008, High performance NoC architecture for two hidden layers BP neural network. in 2008 International SoC Design Conference, ISOCC 2008., 4815624, 2008 International SoC Design Conference, ISOCC 2008, vol. 1, pp. I269-I272, 2008 International SoC Design Conference, ISOCC 2008, Busan, Korea, Republic of, 08/11/24. https://doi.org/10.1109/SOCDC.2008.4815624

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title = "High performance NoC architecture for two hidden layers BP neural network",

abstract = "Artificial Neural Networks (ANNs)are widely used in applications of an intelligent system such as pattern recognition, fuzzy system, optimization and control. We have already proposed a novel NoC architecture for different kinds of BPANNs [1][2] and it was shown that the architecture is a promising hardware implementation for Neural Network. However, some problems to be solved are still remained. One of them is performance. In this paper, we propose another NoC architecture, network topology and routing strategy for higher performance. Experimental results by NoC simulator show that this new architecture and routing strategy reduce the communication load, reduce both latency by 7.7% and dynamic power consumption by 10.3% and also improve throughput by 8.1%, all compared with the previous one.",

keywords = "Architecture, Network on Chip, Neural Network",

author = "Yiping Dong and Takahiro Watanabe",

year = "2008",

month = dec,

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doi = "10.1109/SOCDC.2008.4815624",

language = "English",

isbn = "9781424425990",

series = "2008 International SoC Design Conference, ISOCC 2008",

pages = "I269--I272",

booktitle = "2008 International SoC Design Conference, ISOCC 2008",

note = "2008 International SoC Design Conference, ISOCC 2008 ; Conference date: 24-11-2008 Through 25-11-2008",

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TY - GEN

T1 - High performance NoC architecture for two hidden layers BP neural network

AU - Dong, Yiping

AU - Watanabe, Takahiro

PY - 2008/12/1

Y1 - 2008/12/1

N2 - Artificial Neural Networks (ANNs)are widely used in applications of an intelligent system such as pattern recognition, fuzzy system, optimization and control. We have already proposed a novel NoC architecture for different kinds of BPANNs [1][2] and it was shown that the architecture is a promising hardware implementation for Neural Network. However, some problems to be solved are still remained. One of them is performance. In this paper, we propose another NoC architecture, network topology and routing strategy for higher performance. Experimental results by NoC simulator show that this new architecture and routing strategy reduce the communication load, reduce both latency by 7.7% and dynamic power consumption by 10.3% and also improve throughput by 8.1%, all compared with the previous one.

AB - Artificial Neural Networks (ANNs)are widely used in applications of an intelligent system such as pattern recognition, fuzzy system, optimization and control. We have already proposed a novel NoC architecture for different kinds of BPANNs [1][2] and it was shown that the architecture is a promising hardware implementation for Neural Network. However, some problems to be solved are still remained. One of them is performance. In this paper, we propose another NoC architecture, network topology and routing strategy for higher performance. Experimental results by NoC simulator show that this new architecture and routing strategy reduce the communication load, reduce both latency by 7.7% and dynamic power consumption by 10.3% and also improve throughput by 8.1%, all compared with the previous one.

KW - Architecture

KW - Network on Chip

KW - Neural Network

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High performance NoC architecture for two hidden layers BP neural network

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

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