TY - JOUR
T1 - High profile intra prediction architecture for UHD H.264 Decoder
AU - He, Xun
AU - Zhou, Dajiang
AU - Zhou, Jinjia
AU - Goto, Satoshi
PY - 2010
Y1 - 2010
N2 - This paper presents a new architecture for high profile intra prediction in H.264/AVC video coding standard. Our goal is to design an Intra prediction engine for 4Kx2K@60fps Ultra High Definition (UHD) Decoder. The proposed architecture can provide very stable throughput, which can predict any H.264 intra prediction mode within 66 cycles. Compared with previous design, this feature can guarantee the whole decoding pipeline to work efficiently. The intra prediction engine is divided into two parallel pipelines, one is used for 4x4 block prediction loops and the other is used to prepare data for MB loops. It can overlap data preparing time with prediction time, which can finish data loading and storing within 2 cycles. Comparing with MB pipeline only architecture, it can achieve more than 3.2 times higher throughput with 29.8 K gates cost. The proposed architecture is verified to work at 175 MHz for our UHD Decoder by using TSMC 90 G.
AB - This paper presents a new architecture for high profile intra prediction in H.264/AVC video coding standard. Our goal is to design an Intra prediction engine for 4Kx2K@60fps Ultra High Definition (UHD) Decoder. The proposed architecture can provide very stable throughput, which can predict any H.264 intra prediction mode within 66 cycles. Compared with previous design, this feature can guarantee the whole decoding pipeline to work efficiently. The intra prediction engine is divided into two parallel pipelines, one is used for 4x4 block prediction loops and the other is used to prepare data for MB loops. It can overlap data preparing time with prediction time, which can finish data loading and storing within 2 cycles. Comparing with MB pipeline only architecture, it can achieve more than 3.2 times higher throughput with 29.8 K gates cost. The proposed architecture is verified to work at 175 MHz for our UHD Decoder by using TSMC 90 G.
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U2 - 10.2197/ipsjtsldm.3.303
DO - 10.2197/ipsjtsldm.3.303
M3 - Article
AN - SCOPUS:79954476191
SN - 1882-6687
VL - 3
SP - 303
EP - 313
JO - IPSJ Transactions on System LSI Design Methodology
JF - IPSJ Transactions on System LSI Design Methodology
ER -