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High speed page mode sensing scheme for EPROM's and flash EEPROM's using divided bit line architecture
Yasushi Terada*, Takeshi Nakayama, Kazuo Kobayashi, Masanori Hayashikoshi, Shin ichi Kobayashi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Tsutomu Yoshihara
*Corresponding author for this work
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution