TY - GEN
T1 - High-throughput decoder for low-density parity-check code
AU - Ishikawa, Tatsuyuki
AU - Shimizu, Kazunori
AU - Ikenaga, Takeshi
AU - Goto, Satoshi
N1 - Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2006
Y1 - 2006
N2 - We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304bit regular LDPC codes using modified min-sum algorithm. The decoder achieves a throughput of 530Mb/s at an operating frequency of 147MHz. The chip has been fabricated in a 0.18μm, 6 metal-layer CMOS technology. The chip size is 36mm2.
AB - We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304bit regular LDPC codes using modified min-sum algorithm. The decoder achieves a throughput of 530Mb/s at an operating frequency of 147MHz. The chip has been fabricated in a 0.18μm, 6 metal-layer CMOS technology. The chip size is 36mm2.
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UR - http://www.scopus.com/inward/citedby.url?scp=33748611888&partnerID=8YFLogxK
U2 - 10.1145/1118299.1118332
DO - 10.1145/1118299.1118332
M3 - Conference contribution
AN - SCOPUS:33748611888
SN - 0780394518
SN - 9780780394513
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 112
EP - 113
BT - Proceedings of the ASP-DAC 2006
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
Y2 - 24 January 2006 through 27 January 2006
ER -