High throughput evaluation of SHA-1 implementation using unfolding transformation

Shamsiah Binti Suhaili*, Takahiro Watanabe

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)


Hash Function is widely used in the protocol scheme. In this paper, the design of SHA-1 hash function by using Verilog HDL based on FPGA is studied to optimise both hardware resource and performance. It was successfully synthesised and implemented using Altera Quartus II Arria II GX: EP2AGX45DF29C4. In this paper, two types of design are proposed, namely SHA-1 and SHA-1unfolding. The maximum frequency of SHA-1 design is 274.2 MHz which is higher than SHA-1 unfolding that has the maximum frequency of only 174.73 MHz. However, this leads to a high throughput of the SHA1 unfolding design with 2236.54 Mbps. Besides, both designs provide a small area implementation on Arria II that requires only 423 and 548 Combinational ALUTs, 693 and 907 total register respectively.

Original languageEnglish
Pages (from-to)3350-3355
Number of pages6
JournalARPN Journal of Engineering and Applied Sciences
Issue number5
Publication statusPublished - 2016 Mar 1


  • FPGA
  • HDL
  • Maximum frequency
  • SHA-1

ASJC Scopus subject areas

  • Engineering(all)


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