Highly energy-efficient SRAM with hierarchical bit line charge-sharing method using non-selected bit line charges

Shinji Miyano; Shinichi Moriwaki; Yasue Yamamoto; Atsushi Kawasumi; Toshikazu Suzuki; Takayasu Sakurai; Hirofumi Shinohara

doi:10.1109/JSSC.2012.2237572

Highly energy-efficient SRAM with hierarchical bit line charge-sharing method using non-selected bit line charges

Shinji Miyano^*, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

14 Citations (Scopus)

Abstract

Low voltage SRAM at a near-threshold voltage has two major sources of power waste: excess bit line swing due to the random variation of transistors and dynamic power consumption of the bit line swing of non-selected columns. In order to overcome these waste power consumption issues and achieve the highest energy-efficient operation of low voltage SRAM, the new CSHBL technique and CCC techniques, which is the improved version of the CSHBL, have been proposed. An SRAM fabricated using 65 nm technology adopting the CSHBL achieved an energy consumption of 26.4 pJ/Access/Mbit, and that of 13.8 pJ/Acess/Mbit is achieved by the SRAM macro that adopted CCC with 40 nm technology. This energy consumption is lower than values in previous works.

Original language	English
Article number	6416957
Pages (from-to)	924-931
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	48
Issue number	4
DOIs	https://doi.org/10.1109/JSSC.2012.2237572
Publication status	Published - 2013
Externally published	Yes

Keywords

Charge share
SRAM
low power
low voltage

ASJC Scopus subject areas

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/JSSC.2012.2237572

Cite this

@article{30760736923c429bbffaec8fc0665aee,

title = "Highly energy-efficient SRAM with hierarchical bit line charge-sharing method using non-selected bit line charges",

abstract = "Low voltage SRAM at a near-threshold voltage has two major sources of power waste: excess bit line swing due to the random variation of transistors and dynamic power consumption of the bit line swing of non-selected columns. In order to overcome these waste power consumption issues and achieve the highest energy-efficient operation of low voltage SRAM, the new CSHBL technique and CCC techniques, which is the improved version of the CSHBL, have been proposed. An SRAM fabricated using 65 nm technology adopting the CSHBL achieved an energy consumption of 26.4 pJ/Access/Mbit, and that of 13.8 pJ/Acess/Mbit is achieved by the SRAM macro that adopted CCC with 40 nm technology. This energy consumption is lower than values in previous works.",

keywords = "Charge share, SRAM, low power, low voltage",

author = "Shinji Miyano and Shinichi Moriwaki and Yasue Yamamoto and Atsushi Kawasumi and Toshikazu Suzuki and Takayasu Sakurai and Hirofumi Shinohara",

year = "2013",

doi = "10.1109/JSSC.2012.2237572",

language = "English",

volume = "48",

pages = "924--931",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - Highly energy-efficient SRAM with hierarchical bit line charge-sharing method using non-selected bit line charges

AU - Miyano, Shinji

AU - Moriwaki, Shinichi

AU - Yamamoto, Yasue

AU - Kawasumi, Atsushi

AU - Suzuki, Toshikazu

AU - Sakurai, Takayasu

AU - Shinohara, Hirofumi

PY - 2013

Y1 - 2013

N2 - Low voltage SRAM at a near-threshold voltage has two major sources of power waste: excess bit line swing due to the random variation of transistors and dynamic power consumption of the bit line swing of non-selected columns. In order to overcome these waste power consumption issues and achieve the highest energy-efficient operation of low voltage SRAM, the new CSHBL technique and CCC techniques, which is the improved version of the CSHBL, have been proposed. An SRAM fabricated using 65 nm technology adopting the CSHBL achieved an energy consumption of 26.4 pJ/Access/Mbit, and that of 13.8 pJ/Acess/Mbit is achieved by the SRAM macro that adopted CCC with 40 nm technology. This energy consumption is lower than values in previous works.

AB - Low voltage SRAM at a near-threshold voltage has two major sources of power waste: excess bit line swing due to the random variation of transistors and dynamic power consumption of the bit line swing of non-selected columns. In order to overcome these waste power consumption issues and achieve the highest energy-efficient operation of low voltage SRAM, the new CSHBL technique and CCC techniques, which is the improved version of the CSHBL, have been proposed. An SRAM fabricated using 65 nm technology adopting the CSHBL achieved an energy consumption of 26.4 pJ/Access/Mbit, and that of 13.8 pJ/Acess/Mbit is achieved by the SRAM macro that adopted CCC with 40 nm technology. This energy consumption is lower than values in previous works.

KW - Charge share

KW - SRAM

KW - low power

KW - low voltage

UR - http://www.scopus.com/inward/record.url?scp=84875717574&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84875717574&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2012.2237572

DO - 10.1109/JSSC.2012.2237572

M3 - Article

AN - SCOPUS:84875717574

SN - 0018-9200

VL - 48

SP - 924

EP - 931

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 4

M1 - 6416957

ER -

Highly energy-efficient SRAM with hierarchical bit line charge-sharing method using non-selected bit line charges

Abstract

Keywords

ASJC Scopus subject areas

UN SDGs

Access to Document

Other files and links

Fingerprint

Cite this