Impact of 0.10 μm SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology

Y. Hirano; T. Matsumoto; S. Maeda; T. Iwamatsu; T. Kunikiyo; K. Nii; K. Yamamoto; Y. Yamaguchi; T. Ipposhi; S. Maegawa; M. Inuishi

Impact of 0.10 μm SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology

Y. Hirano^*, T. Matsumoto, S. Maeda, T. Iwamatsu, T. Kunikiyo, K. Nii, K. Yamamoto, Y. Yamaguchi, T. Ipposhi, S. Maegawa, M. Inuishi

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

28 Citations (Scopus)

Abstract

A hybrid-trench-isolation (HTI) technology is proposed to overcome the scaling limitations caused by the difficulty of gate thinning and increased soft error rate at the 0.1 μm era. It is revealed that a significant speed improvement against bulk is achieved by using the body-tied structure without floating-body-related speed deterioration. A two-order reduction in the soft error rate for an HTI-SOI 4M-bit SRAM was demonstrated as compared with bulk one. Moreover, it is presented that full trench isolation in the HTI offers excellent isolation characteristics to realize the one-chip integration of analog and digital LSI's. It is concluded that SOI technology with the HTI structure is one of the solutions against the scaling limitations.

Original language	English
Pages (from-to)	467-470
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 2000
Externally published	Yes
Event	2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States Duration: 2000 Dec 10 → 2000 Dec 13

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

@article{022ef74f923f45f8aa223021a1d859c5,

title = "Impact of 0.10 μm SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology",

abstract = "A hybrid-trench-isolation (HTI) technology is proposed to overcome the scaling limitations caused by the difficulty of gate thinning and increased soft error rate at the 0.1 μm era. It is revealed that a significant speed improvement against bulk is achieved by using the body-tied structure without floating-body-related speed deterioration. A two-order reduction in the soft error rate for an HTI-SOI 4M-bit SRAM was demonstrated as compared with bulk one. Moreover, it is presented that full trench isolation in the HTI offers excellent isolation characteristics to realize the one-chip integration of analog and digital LSI's. It is concluded that SOI technology with the HTI structure is one of the solutions against the scaling limitations.",

author = "Y. Hirano and T. Matsumoto and S. Maeda and T. Iwamatsu and T. Kunikiyo and K. Nii and K. Yamamoto and Y. Yamaguchi and T. Ipposhi and S. Maegawa and M. Inuishi",

year = "2000",

language = "English",

pages = "467--470",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2000 IEEE International Electron Devices Meeting ; Conference date: 10-12-2000 Through 13-12-2000",

}

TY - JOUR

T1 - Impact of 0.10 μm SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology

AU - Hirano, Y.

AU - Matsumoto, T.

AU - Maeda, S.

AU - Iwamatsu, T.

AU - Kunikiyo, T.

AU - Nii, K.

AU - Yamamoto, K.

AU - Yamaguchi, Y.

AU - Ipposhi, T.

AU - Maegawa, S.

AU - Inuishi, M.

PY - 2000

Y1 - 2000

N2 - A hybrid-trench-isolation (HTI) technology is proposed to overcome the scaling limitations caused by the difficulty of gate thinning and increased soft error rate at the 0.1 μm era. It is revealed that a significant speed improvement against bulk is achieved by using the body-tied structure without floating-body-related speed deterioration. A two-order reduction in the soft error rate for an HTI-SOI 4M-bit SRAM was demonstrated as compared with bulk one. Moreover, it is presented that full trench isolation in the HTI offers excellent isolation characteristics to realize the one-chip integration of analog and digital LSI's. It is concluded that SOI technology with the HTI structure is one of the solutions against the scaling limitations.

AB - A hybrid-trench-isolation (HTI) technology is proposed to overcome the scaling limitations caused by the difficulty of gate thinning and increased soft error rate at the 0.1 μm era. It is revealed that a significant speed improvement against bulk is achieved by using the body-tied structure without floating-body-related speed deterioration. A two-order reduction in the soft error rate for an HTI-SOI 4M-bit SRAM was demonstrated as compared with bulk one. Moreover, it is presented that full trench isolation in the HTI offers excellent isolation characteristics to realize the one-chip integration of analog and digital LSI's. It is concluded that SOI technology with the HTI structure is one of the solutions against the scaling limitations.

UR - http://www.scopus.com/inward/record.url?scp=17344383097&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=17344383097&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:17344383097

SN - 0163-1918

SP - 467

EP - 470

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - 2000 IEEE International Electron Devices Meeting

Y2 - 10 December 2000 through 13 December 2000

ER -

Impact of 0.10 μm SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology

Abstract

ASJC Scopus subject areas

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