Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond

T. Yamashita; K. Shiga; T. Hayashi; H. Umeda; H. Oda; T. Eimori; M. Inuishi; Y. Ohji; K. Eriguchi; K. Nakanishi; H. Nakaoka; T. Yamada; M. Nakamura; I. Miyanaga; A. Kajiya; M. Kubota; M. Ogura

doi:10.1109/IMFEDK.2004.1566439

Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond

T. Yamashita, K. Shiga, T. Hayashi, H. Umeda, H. Oda, T. Eimori, M. Inuishi, Y. Ohji, K. Eriguchi, K. Nakanishi, H. Nakaoka, T. Yamada, M. Nakamura, I. Miyanaga, A. Kajiya, M. Kubota, M. Ogura

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

For scaled CMOSFETs, it becomes much more difficult to ensure sufficient reliability of gate-oxide film, since power supply voltage is not scaled proportionally with gate-oxide. As well as the increase of the electrical stress that put on the gate-oxide, miniaturization effect should be cared. This paper demonstrates the performance of 65-nm node CMOSFETs, focused on gate oxide reliability, which is found to become crucial issue for short-channel pMOSFETs. Boron penetration from S/D-extension is found to increase gate leakage current and degrade gate oxide integrity. Fabrication process that suppresses the boron penetration is discussed, and optimized transistor characteristics for low operational power (LOP) and low standby power (LSTP) devices are presented.

Original language	English
Title of host publication	IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai
Editors	Hiroshi Nozawa
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	123-124
Number of pages	2
ISBN (Electronic)	0780384237, 9780780384231
DOIs	https://doi.org/10.1109/IMFEDK.2004.1566439
Publication status	Published - 2004
Externally published	Yes
Event	2nd International Meeting for Future of Electron Devices, Kansai, IMFEDK 2004 - Kyoto, Japan Duration: 2004 Jul 26 → 2004 Jul 28

Publication series

Name	IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai

Other

Other	2nd International Meeting for Future of Electron Devices, Kansai, IMFEDK 2004
Country/Territory	Japan
City	Kyoto
Period	04/7/26 → 04/7/28

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/IMFEDK.2004.1566439

Cite this

Yamashita, T., Shiga, K., Hayashi, T., Umeda, H., Oda, H., Eimori, T., Inuishi, M., Ohji, Y., Eriguchi, K., Nakanishi, K., Nakaoka, H., Yamada, T., Nakamura, M., Miyanaga, I., Kajiya, A., Kubota, M., & Ogura, M. (2004). Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond. In H. Nozawa (Ed.), IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai (pp. 123-124). Article 1566439 (IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IMFEDK.2004.1566439

Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond. / Yamashita, T.; Shiga, K.; Hayashi, T. et al.
IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai. ed. / Hiroshi Nozawa. Institute of Electrical and Electronics Engineers Inc., 2004. p. 123-124 1566439 (IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yamashita, T, Shiga, K, Hayashi, T, Umeda, H, Oda, H, Eimori, T, Inuishi, M, Ohji, Y, Eriguchi, K, Nakanishi, K, Nakaoka, H, Yamada, T, Nakamura, M, Miyanaga, I, Kajiya, A, Kubota, M & Ogura, M 2004, Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond. in H Nozawa (ed.), IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai., 1566439, IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai, Institute of Electrical and Electronics Engineers Inc., pp. 123-124, 2nd International Meeting for Future of Electron Devices, Kansai, IMFEDK 2004, Kyoto, Japan, 04/7/26. https://doi.org/10.1109/IMFEDK.2004.1566439

Yamashita T, Shiga K, Hayashi T, Umeda H, Oda H, Eimori T et al. Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond. In Nozawa H, editor, IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai. Institute of Electrical and Electronics Engineers Inc. 2004. p. 123-124. 1566439. (IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai). doi: 10.1109/IMFEDK.2004.1566439

Yamashita, T. ; Shiga, K. ; Hayashi, T. et al. / Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond. IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai. editor / Hiroshi Nozawa. Institute of Electrical and Electronics Engineers Inc., 2004. pp. 123-124 (IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai).

@inproceedings{e78ab3c898a1405e9d6df2bd3ebcaee4,

title = "Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond",

abstract = "For scaled CMOSFETs, it becomes much more difficult to ensure sufficient reliability of gate-oxide film, since power supply voltage is not scaled proportionally with gate-oxide. As well as the increase of the electrical stress that put on the gate-oxide, miniaturization effect should be cared. This paper demonstrates the performance of 65-nm node CMOSFETs, focused on gate oxide reliability, which is found to become crucial issue for short-channel pMOSFETs. Boron penetration from S/D-extension is found to increase gate leakage current and degrade gate oxide integrity. Fabrication process that suppresses the boron penetration is discussed, and optimized transistor characteristics for low operational power (LOP) and low standby power (LSTP) devices are presented.",

author = "T. Yamashita and K. Shiga and T. Hayashi and H. Umeda and H. Oda and T. Eimori and M. Inuishi and Y. Ohji and K. Eriguchi and K. Nakanishi and H. Nakaoka and T. Yamada and M. Nakamura and I. Miyanaga and A. Kajiya and M. Kubota and M. Ogura",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE. Copyright: Copyright 2016 Elsevier B.V., All rights reserved.; 2nd International Meeting for Future of Electron Devices, Kansai, IMFEDK 2004 ; Conference date: 26-07-2004 Through 28-07-2004",

year = "2004",

doi = "10.1109/IMFEDK.2004.1566439",

language = "English",

series = "IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "123--124",

editor = "Hiroshi Nozawa",

booktitle = "IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai",

}

TY - GEN

T1 - Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond

AU - Yamashita, T.

AU - Shiga, K.

AU - Hayashi, T.

AU - Umeda, H.

AU - Oda, H.

AU - Eimori, T.

AU - Inuishi, M.

AU - Ohji, Y.

AU - Eriguchi, K.

AU - Nakanishi, K.

AU - Nakaoka, H.

AU - Yamada, T.

AU - Nakamura, M.

AU - Miyanaga, I.

AU - Kajiya, A.

AU - Kubota, M.

AU - Ogura, M.

PY - 2004

Y1 - 2004

N2 - For scaled CMOSFETs, it becomes much more difficult to ensure sufficient reliability of gate-oxide film, since power supply voltage is not scaled proportionally with gate-oxide. As well as the increase of the electrical stress that put on the gate-oxide, miniaturization effect should be cared. This paper demonstrates the performance of 65-nm node CMOSFETs, focused on gate oxide reliability, which is found to become crucial issue for short-channel pMOSFETs. Boron penetration from S/D-extension is found to increase gate leakage current and degrade gate oxide integrity. Fabrication process that suppresses the boron penetration is discussed, and optimized transistor characteristics for low operational power (LOP) and low standby power (LSTP) devices are presented.

AB - For scaled CMOSFETs, it becomes much more difficult to ensure sufficient reliability of gate-oxide film, since power supply voltage is not scaled proportionally with gate-oxide. As well as the increase of the electrical stress that put on the gate-oxide, miniaturization effect should be cared. This paper demonstrates the performance of 65-nm node CMOSFETs, focused on gate oxide reliability, which is found to become crucial issue for short-channel pMOSFETs. Boron penetration from S/D-extension is found to increase gate leakage current and degrade gate oxide integrity. Fabrication process that suppresses the boron penetration is discussed, and optimized transistor characteristics for low operational power (LOP) and low standby power (LSTP) devices are presented.

UR - http://www.scopus.com/inward/record.url?scp=84934290261&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84934290261&partnerID=8YFLogxK

U2 - 10.1109/IMFEDK.2004.1566439

DO - 10.1109/IMFEDK.2004.1566439

M3 - Conference contribution

AN - SCOPUS:84934290261

T3 - IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai

SP - 123

EP - 124

BT - IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai

A2 - Nozawa, Hiroshi

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2nd International Meeting for Future of Electron Devices, Kansai, IMFEDK 2004

Y2 - 26 July 2004 through 28 July 2004

ER -

Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this