Impact of boron penetration from S/D-extension on gate-Oxide reliability for 65-nm node CMOS and beyond

T. Yamashita*, K. Ota, K. Shiga, T. Hayashi, H. Umeda, H. Oda, T. Eimori, M. Inuishi, Y. Ohji, K. Eriguchi, K. Nakanishi, H. Nakaoka, T. Yamada, M. Nakamura, I. Miyanaga, A. Kajiya, M. Kubota, M. Ogura

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

6 Citations (Scopus)


Nitridation technique of the gate-oxide top surface has been much studied to suppress the boron penetration from the doped gate poly-silicon and proved to be efficient against NBTI degradation. However there is another path for boron to penetrate to gate-oxide from the substrate, where this technique is helpless. We found that boron penetration from the S/D-extension becomes crucial issue on gate leakage and gate-oxide integrity especially for deep sub-micron pMOS, where stress from the sidewall and interlayer dielectrics accelerates to deteriorate those gate-oxide characteristics. We demonstrate that nitridation after gate etching is very efficient to control this new degradation mode. We also propose the totally-optimized transistor structure for nMOS and pMOS, which shows sufficient electrical property and reliability for low operational power (LOP) and low standby power (LSTP) of 65-nm node and beyond.

Original languageEnglish
Pages (from-to)136-137
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
Publication statusPublished - 2004
Externally publishedYes
Event2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States
Duration: 2004 Jun 152004 Jun 17

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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