Impact of boron penetration from S/D-extension on gate-Oxide reliability for 65-nm node CMOS and beyond

T. Yamashita; K. Ota; K. Shiga; T. Hayashi; H. Umeda; H. Oda; T. Eimori; M. Inuishi; Y. Ohji; K. Eriguchi; K. Nakanishi; H. Nakaoka; T. Yamada; M. Nakamura; I. Miyanaga; A. Kajiya; M. Kubota; M. Ogura

doi:10.1109/vlsit.2004.1345438

Impact of boron penetration from S/D-extension on gate-Oxide reliability for 65-nm node CMOS and beyond

T. Yamashita^*, K. Ota, K. Shiga, T. Hayashi, H. Umeda, H. Oda, T. Eimori, M. Inuishi, Y. Ohji, K. Eriguchi, K. Nakanishi, H. Nakaoka, T. Yamada, M. Nakamura, I. Miyanaga, A. Kajiya, M. Kubota, M. Ogura

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

6 Citations (Scopus)

Abstract

Nitridation technique of the gate-oxide top surface has been much studied to suppress the boron penetration from the doped gate poly-silicon and proved to be efficient against NBTI degradation. However there is another path for boron to penetrate to gate-oxide from the substrate, where this technique is helpless. We found that boron penetration from the S/D-extension becomes crucial issue on gate leakage and gate-oxide integrity especially for deep sub-micron pMOS, where stress from the sidewall and interlayer dielectrics accelerates to deteriorate those gate-oxide characteristics. We demonstrate that nitridation after gate etching is very efficient to control this new degradation mode. We also propose the totally-optimized transistor structure for nMOS and pMOS, which shows sufficient electrical property and reliability for low operational power (LOP) and low standby power (LSTP) of 65-nm node and beyond.

Original language	English
Pages (from-to)	136-137
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
DOIs	https://doi.org/10.1109/vlsit.2004.1345438
Publication status	Published - 2004
Externally published	Yes
Event	2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States Duration: 2004 Jun 15 → 2004 Jun 17

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/vlsit.2004.1345438

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Yamashita, T., Ota, K., Shiga, K., Hayashi, T., Umeda, H., Oda, H., Eimori, T., Inuishi, M., Ohji, Y., Eriguchi, K., Nakanishi, K., Nakaoka, H., Yamada, T., Nakamura, M., Miyanaga, I., Kajiya, A., Kubota, M., & Ogura, M. (2004). Impact of boron penetration from S/D-extension on gate-Oxide reliability for 65-nm node CMOS and beyond. Digest of Technical Papers - Symposium on VLSI Technology, 136-137. https://doi.org/10.1109/vlsit.2004.1345438

Yamashita, T, Ota, K, Shiga, K, Hayashi, T, Umeda, H, Oda, H, Eimori, T, Inuishi, M, Ohji, Y, Eriguchi, K, Nakanishi, K, Nakaoka, H, Yamada, T, Nakamura, M, Miyanaga, I, Kajiya, A, Kubota, M & Ogura, M 2004, 'Impact of boron penetration from S/D-extension on gate-Oxide reliability for 65-nm node CMOS and beyond', Digest of Technical Papers - Symposium on VLSI Technology, pp. 136-137. https://doi.org/10.1109/vlsit.2004.1345438

@article{1525f75de9804c628b9914f2bc5ede94,

title = "Impact of boron penetration from S/D-extension on gate-Oxide reliability for 65-nm node CMOS and beyond",

abstract = "Nitridation technique of the gate-oxide top surface has been much studied to suppress the boron penetration from the doped gate poly-silicon and proved to be efficient against NBTI degradation. However there is another path for boron to penetrate to gate-oxide from the substrate, where this technique is helpless. We found that boron penetration from the S/D-extension becomes crucial issue on gate leakage and gate-oxide integrity especially for deep sub-micron pMOS, where stress from the sidewall and interlayer dielectrics accelerates to deteriorate those gate-oxide characteristics. We demonstrate that nitridation after gate etching is very efficient to control this new degradation mode. We also propose the totally-optimized transistor structure for nMOS and pMOS, which shows sufficient electrical property and reliability for low operational power (LOP) and low standby power (LSTP) of 65-nm node and beyond.",

author = "T. Yamashita and K. Ota and K. Shiga and T. Hayashi and H. Umeda and H. Oda and T. Eimori and M. Inuishi and Y. Ohji and K. Eriguchi and K. Nakanishi and H. Nakaoka and T. Yamada and M. Nakamura and I. Miyanaga and A. Kajiya and M. Kubota and M. Ogura",

year = "2004",

doi = "10.1109/vlsit.2004.1345438",

language = "English",

pages = "136--137",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

issn = "0743-1562",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Impact of boron penetration from S/D-extension on gate-Oxide reliability for 65-nm node CMOS and beyond

AU - Yamashita, T.

AU - Ota, K.

AU - Shiga, K.

AU - Hayashi, T.

AU - Umeda, H.

AU - Oda, H.

AU - Eimori, T.

AU - Inuishi, M.

AU - Ohji, Y.

AU - Eriguchi, K.

AU - Nakanishi, K.

AU - Nakaoka, H.

AU - Yamada, T.

AU - Nakamura, M.

AU - Miyanaga, I.

AU - Kajiya, A.

AU - Kubota, M.

AU - Ogura, M.

PY - 2004

Y1 - 2004

N2 - Nitridation technique of the gate-oxide top surface has been much studied to suppress the boron penetration from the doped gate poly-silicon and proved to be efficient against NBTI degradation. However there is another path for boron to penetrate to gate-oxide from the substrate, where this technique is helpless. We found that boron penetration from the S/D-extension becomes crucial issue on gate leakage and gate-oxide integrity especially for deep sub-micron pMOS, where stress from the sidewall and interlayer dielectrics accelerates to deteriorate those gate-oxide characteristics. We demonstrate that nitridation after gate etching is very efficient to control this new degradation mode. We also propose the totally-optimized transistor structure for nMOS and pMOS, which shows sufficient electrical property and reliability for low operational power (LOP) and low standby power (LSTP) of 65-nm node and beyond.

AB - Nitridation technique of the gate-oxide top surface has been much studied to suppress the boron penetration from the doped gate poly-silicon and proved to be efficient against NBTI degradation. However there is another path for boron to penetrate to gate-oxide from the substrate, where this technique is helpless. We found that boron penetration from the S/D-extension becomes crucial issue on gate leakage and gate-oxide integrity especially for deep sub-micron pMOS, where stress from the sidewall and interlayer dielectrics accelerates to deteriorate those gate-oxide characteristics. We demonstrate that nitridation after gate etching is very efficient to control this new degradation mode. We also propose the totally-optimized transistor structure for nMOS and pMOS, which shows sufficient electrical property and reliability for low operational power (LOP) and low standby power (LSTP) of 65-nm node and beyond.

UR - http://www.scopus.com/inward/record.url?scp=4544283772&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=4544283772&partnerID=8YFLogxK

U2 - 10.1109/vlsit.2004.1345438

DO - 10.1109/vlsit.2004.1345438

M3 - Conference article

AN - SCOPUS:4544283772

SN - 0743-1562

SP - 136

EP - 137

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

T2 - 2004 Symposium on VLSI Technology - Digest of Technical Papers

Y2 - 15 June 2004 through 17 June 2004

ER -

Impact of boron penetration from S/D-extension on gate-Oxide reliability for 65-nm node CMOS and beyond

Abstract

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