Implementation of LDPC decoder for 802.16e

Xiao Peng*, Satoshi Goto

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)


The implementation complexity of the decoder for Low-density Parity-check Codes (LDPC) is dictated by memory and interconnection requirements. In this paper, we investigate the approaches to realize Turbo Decoding Message Passing (TDMP) algorithm. We compare the performance and implementation complexity of original approach, Jacobian approach, normalized min-sum approach and offset min-sum approach which are targeted for QuasiCyclic (QC) LDPC code defined in IEEE 802.16e standard. The normalized and offset approaches are more suitable for hardware implementation, which are realized on the FPGA.

Original languageEnglish
Title of host publicationASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC
Number of pages4
Publication statusPublished - 2009
Event2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha
Duration: 2009 Oct 202009 Oct 23


Other2009 8th IEEE International Conference on ASIC, ASICON 2009


  • LDPC
  • Min-sum
  • TDMP

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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