Implementation of LDPC decoder for 802.16e

Xiao Peng; Satoshi Goto

doi:10.1109/ASICON.2009.5351628

Implementation of LDPC decoder for 802.16e

Xiao Peng^*, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

The implementation complexity of the decoder for Low-density Parity-check Codes (LDPC) is dictated by memory and interconnection requirements. In this paper, we investigate the approaches to realize Turbo Decoding Message Passing (TDMP) algorithm. We compare the performance and implementation complexity of original approach, Jacobian approach, normalized min-sum approach and offset min-sum approach which are targeted for QuasiCyclic (QC) LDPC code defined in IEEE 802.16e standard. The normalized and offset approaches are more suitable for hardware implementation, which are realized on the FPGA.

Original language	English
Title of host publication	ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC
Pages	501-504
Number of pages	4
DOIs	https://doi.org/10.1109/ASICON.2009.5351628
Publication status	Published - 2009
Event	2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha Duration: 2009 Oct 20 → 2009 Oct 23

Other

Other	2009 8th IEEE International Conference on ASIC, ASICON 2009
City	Changsha
Period	09/10/20 → 09/10/23

Keywords

LDPC
Min-sum
TDMP

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASICON.2009.5351628

Cite this

@inproceedings{4126feecc6304a09b6bb5f3429a317d4,

title = "Implementation of LDPC decoder for 802.16e",

abstract = "The implementation complexity of the decoder for Low-density Parity-check Codes (LDPC) is dictated by memory and interconnection requirements. In this paper, we investigate the approaches to realize Turbo Decoding Message Passing (TDMP) algorithm. We compare the performance and implementation complexity of original approach, Jacobian approach, normalized min-sum approach and offset min-sum approach which are targeted for QuasiCyclic (QC) LDPC code defined in IEEE 802.16e standard. The normalized and offset approaches are more suitable for hardware implementation, which are realized on the FPGA.",

keywords = "LDPC, Min-sum, TDMP",

author = "Xiao Peng and Satoshi Goto",

year = "2009",

doi = "10.1109/ASICON.2009.5351628",

language = "English",

isbn = "9781424438686",

pages = "501--504",

booktitle = "ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC",

note = "2009 8th IEEE International Conference on ASIC, ASICON 2009 ; Conference date: 20-10-2009 Through 23-10-2009",

}

TY - GEN

T1 - Implementation of LDPC decoder for 802.16e

AU - Peng, Xiao

AU - Goto, Satoshi

PY - 2009

Y1 - 2009

N2 - The implementation complexity of the decoder for Low-density Parity-check Codes (LDPC) is dictated by memory and interconnection requirements. In this paper, we investigate the approaches to realize Turbo Decoding Message Passing (TDMP) algorithm. We compare the performance and implementation complexity of original approach, Jacobian approach, normalized min-sum approach and offset min-sum approach which are targeted for QuasiCyclic (QC) LDPC code defined in IEEE 802.16e standard. The normalized and offset approaches are more suitable for hardware implementation, which are realized on the FPGA.

AB - The implementation complexity of the decoder for Low-density Parity-check Codes (LDPC) is dictated by memory and interconnection requirements. In this paper, we investigate the approaches to realize Turbo Decoding Message Passing (TDMP) algorithm. We compare the performance and implementation complexity of original approach, Jacobian approach, normalized min-sum approach and offset min-sum approach which are targeted for QuasiCyclic (QC) LDPC code defined in IEEE 802.16e standard. The normalized and offset approaches are more suitable for hardware implementation, which are realized on the FPGA.

KW - LDPC

KW - Min-sum

KW - TDMP

UR - http://www.scopus.com/inward/record.url?scp=77949387843&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77949387843&partnerID=8YFLogxK

U2 - 10.1109/ASICON.2009.5351628

DO - 10.1109/ASICON.2009.5351628

M3 - Conference contribution

AN - SCOPUS:77949387843

SN - 9781424438686

SP - 501

EP - 504

BT - ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

T2 - 2009 8th IEEE International Conference on ASIC, ASICON 2009

Y2 - 20 October 2009 through 23 October 2009

ER -

Implementation of LDPC decoder for 802.16e

Abstract

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this