Abstract
As process technology is scaling down, timing speculation techniques such as Razor and STEP are emerged as alternative solutions to reduce required margins due to various variation effects. Unlike Razor, STEP is a prediction-based timing speculation method to predict suspicious timing errors before they really appear, and thus it can result in more performance improvement. Therefore, an improved monitoring-path selection algorithm for STEP-based timing speculation is proposed in this paper, in which candidate monitoring-paths are selected based on short path removement and path length estimation. Experimental results show that the proposed algorithm realizes an average of 1.71X overclocking compared with worst-case based designs.
Original language | English |
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Title of host publication | Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781479984831 |
DOIs | |
Publication status | Published - 2016 Jul 19 |
Event | 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China Duration: 2015 Nov 3 → 2015 Nov 6 |
Other
Other | 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 |
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Country/Territory | China |
City | Chengdu |
Period | 15/11/3 → 15/11/6 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering