Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits

Hiroshi Fuketa; Ryo Takahashi; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai

doi:10.1109/CICC.2012.6330689

Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits

Hiroshi Fuketa^*, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Abnormal increase of the crosstalk noise in the sub-threshold logic circuits is found for the first time. When the threshold voltages (V _TH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, the large crosstalk noise is observed, because the on-resistance has an exponential dependence on V_TH in the sub-threshold circuits. In this paper, the large crosstalk noise due to the imbalanced V_TH is measured. A new crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with 1.5-mm wire in a 40-nm CMOS at the power supply voltage (V_DD) of 0.3V, the measured noise amplitude increases from 32% of V_DD to 71% of V_DD, when the imbalanced V _TH is realized by tuning a body bias in pMOS. In the worst case fast-nMOS/slow-pMOS corner simulations, the noise amplitude increases from 47% of V_DD to 68% of V_DD, when V_DD is reduced from 1.1V to 0.3V, which is explained by the proposed model.

Original language	English
Title of host publication	Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012
DOIs	https://doi.org/10.1109/CICC.2012.6330689
Publication status	Published - 2012 Nov 26
Externally published	Yes
Event	34th Annual Custom Integrated Circuits Conference, CICC 2012 - San Jose, CA, United States Duration: 2012 Sept 9 → 2012 Sept 12

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Other

Other	34th Annual Custom Integrated Circuits Conference, CICC 2012
Country/Territory	United States
City	San Jose, CA
Period	12/9/9 → 12/9/12

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2012.6330689

Cite this

Fuketa, H., Takahashi, R., Takamiya, M., Nomura, M., Shinohara, H., & Sakurai, T. (2012). Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. In Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012 Article 6330689 (Proceedings of the Custom Integrated Circuits Conference). https://doi.org/10.1109/CICC.2012.6330689

Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. / Fuketa, Hiroshi; Takahashi, Ryo; Takamiya, Makoto et al.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012. 2012. 6330689 (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fuketa, H, Takahashi, R, Takamiya, M, Nomura, M, Shinohara, H & Sakurai, T 2012, Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. in Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012., 6330689, Proceedings of the Custom Integrated Circuits Conference, 34th Annual Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, United States, 12/9/9. https://doi.org/10.1109/CICC.2012.6330689

Fuketa H, Takahashi R, Takamiya M, Nomura M, Shinohara H, Sakurai T. Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. In Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012. 2012. 6330689. (Proceedings of the Custom Integrated Circuits Conference). doi: 10.1109/CICC.2012.6330689

@inproceedings{96b01a05df304331b8f0d4cc03bd81e7,

title = "Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits",

abstract = "Abnormal increase of the crosstalk noise in the sub-threshold logic circuits is found for the first time. When the threshold voltages (V TH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, the large crosstalk noise is observed, because the on-resistance has an exponential dependence on VTH in the sub-threshold circuits. In this paper, the large crosstalk noise due to the imbalanced VTH is measured. A new crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with 1.5-mm wire in a 40-nm CMOS at the power supply voltage (VDD) of 0.3V, the measured noise amplitude increases from 32% of VDD to 71% of VDD, when the imbalanced V TH is realized by tuning a body bias in pMOS. In the worst case fast-nMOS/slow-pMOS corner simulations, the noise amplitude increases from 47% of VDD to 68% of VDD, when VDD is reduced from 1.1V to 0.3V, which is explained by the proposed model.",

author = "Hiroshi Fuketa and Ryo Takahashi and Makoto Takamiya and Masahiro Nomura and Hirofumi Shinohara and Takayasu Sakurai",

year = "2012",

month = nov,

day = "26",

doi = "10.1109/CICC.2012.6330689",

language = "English",

isbn = "9781467315555",

series = "Proceedings of the Custom Integrated Circuits Conference",

booktitle = "Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012",

note = "34th Annual Custom Integrated Circuits Conference, CICC 2012 ; Conference date: 09-09-2012 Through 12-09-2012",

}

TY - GEN

T1 - Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits

AU - Fuketa, Hiroshi

AU - Takahashi, Ryo

AU - Takamiya, Makoto

AU - Nomura, Masahiro

AU - Shinohara, Hirofumi

AU - Sakurai, Takayasu

PY - 2012/11/26

Y1 - 2012/11/26

N2 - Abnormal increase of the crosstalk noise in the sub-threshold logic circuits is found for the first time. When the threshold voltages (V TH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, the large crosstalk noise is observed, because the on-resistance has an exponential dependence on VTH in the sub-threshold circuits. In this paper, the large crosstalk noise due to the imbalanced VTH is measured. A new crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with 1.5-mm wire in a 40-nm CMOS at the power supply voltage (VDD) of 0.3V, the measured noise amplitude increases from 32% of VDD to 71% of VDD, when the imbalanced V TH is realized by tuning a body bias in pMOS. In the worst case fast-nMOS/slow-pMOS corner simulations, the noise amplitude increases from 47% of VDD to 68% of VDD, when VDD is reduced from 1.1V to 0.3V, which is explained by the proposed model.

AB - Abnormal increase of the crosstalk noise in the sub-threshold logic circuits is found for the first time. When the threshold voltages (V TH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, the large crosstalk noise is observed, because the on-resistance has an exponential dependence on VTH in the sub-threshold circuits. In this paper, the large crosstalk noise due to the imbalanced VTH is measured. A new crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with 1.5-mm wire in a 40-nm CMOS at the power supply voltage (VDD) of 0.3V, the measured noise amplitude increases from 32% of VDD to 71% of VDD, when the imbalanced V TH is realized by tuning a body bias in pMOS. In the worst case fast-nMOS/slow-pMOS corner simulations, the noise amplitude increases from 47% of VDD to 68% of VDD, when VDD is reduced from 1.1V to 0.3V, which is explained by the proposed model.

UR - http://www.scopus.com/inward/record.url?scp=84869444394&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84869444394&partnerID=8YFLogxK

U2 - 10.1109/CICC.2012.6330689

DO - 10.1109/CICC.2012.6330689

M3 - Conference contribution

AN - SCOPUS:84869444394

SN - 9781467315555

T3 - Proceedings of the Custom Integrated Circuits Conference

BT - Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012

T2 - 34th Annual Custom Integrated Circuits Conference, CICC 2012

Y2 - 9 September 2012 through 12 September 2012

ER -

Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits

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