Abstract
As technology advances, 3D ICs are introduced for alleviating the interconnect problem coming with shrinking feature size and increasing integration density. In 3D ICs, one of the key challenges is the vertical interlayer via used for different device layers connection. In this paper, we use min-cost maximum flow algorithm for integrated interlayer via planning and pin assignment for all two-pin nets from one source block to all the other blocks, which make sure interlayer via is inserted as successfully as possible with the shortest wire length. By iteratively using this algorithm with other auxiliary methods on each block, we can deal with the problem for all nets among blocks in 3D ICs. Experimental results show its efficiency and effectiveness. To our knowledge, this is the first algorithm of interlayer via planning with pin assignment for 3D ICs.
| Original language | English |
|---|---|
| Title of host publication | International Workshop on System Level Interconnect Prediction, SLIP |
| Pages | 99-104 |
| Number of pages | 6 |
| DOIs | |
| Publication status | Published - 2009 |
| Event | 2009 ACM/IEEE Workshop on System Level Interconnect Prediction, SLIP'09 - San Francisco, CA Duration: 2009 Jul 26 → 2009 Jul 27 |
Other
| Other | 2009 ACM/IEEE Workshop on System Level Interconnect Prediction, SLIP'09 |
|---|---|
| City | San Francisco, CA |
| Period | 09/7/26 → 09/7/27 |
Keywords
- Algorithms
- B.7.2 [Integrated circuits]: design aids - placement and routing
- Design
- Experimentation
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
- Computer Science Applications
- Applied Mathematics
