Intra prediction architecture for H.264/AVC QFHD encoder

Gang He*, Dajiang Zhou, Jinjia Zhou, Satoshi Goto

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)


This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering can avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 4kx2k encoding can be achieved with negligible quality loss. 16×16 prediction engine and 8×8 prediction engine work parallel for prediction and coefficients generating. A reordering interlaced reconstruction is also designed for fully pipelined architecture. It takes only 160 cycles to process one macroblock (MB). Hardware utilization of prediction and reconstruction modules is almost 100%. Furthermore, PE-reusable 8×8 intra predictor and hybrid SAD & SATD mode decision are proposed to save hardware cost. The design is implemented by 90nm CMOS technology with 113.2k gates and can encode 4kx2k video sequences at 60 fps with operation frequency of 310MHz.

Original languageEnglish
Title of host publication28th Picture Coding Symposium, PCS 2010
Number of pages4
Publication statusPublished - 2010
Event28th Picture Coding Symposium, PCS 2010 - Nagoya
Duration: 2010 Dec 82010 Dec 10


Other28th Picture Coding Symposium, PCS 2010


  • Fukuoka
  • H.264/AVC
  • Hardware architecture 2-7 Hibikino
  • Intra prediction
  • Japan
  • Kitakyushu
  • Wakamatsu-ku

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Vision and Pattern Recognition


Dive into the research topics of 'Intra prediction architecture for H.264/AVC QFHD encoder'. Together they form a unique fingerprint.

Cite this