TY - GEN
T1 - Linear and bi-linear interpolation circuits using selector logics and their evaluations
AU - Shio, Masashi
AU - Yanagisawa, Masao
AU - Togawa, Nozomu
PY - 2014/1/1
Y1 - 2014/1/1
N2 - Interpolation is a technique that presumes a value between existing data, which is often used for image scaling and correction of distortion. Linear interpolation is one of the interpolation techniques which interpolates inbetween values by linearly connecting two known values. Also, bi-linear interpolation is one of interpolation techniques, which interpolates a value linearly from its four circumferences. Both of them are used practically in many cases. In this paper, we propose high-speed and small-sized linear and bi-linear interpolation circuits based on selector logics. The proposed linear and bi-linear interpolation circuits reduce carry propagation delays by using selector logics and then realize fast and small-sized circuits. We have implemented our linear interpolation circuit and bi-linear interpolation circuits in several ways and evaluated each of them. We can find out that a selector-based bi-linear interpolation circuit where its partial products are summed up by using the arithmetic operator saves its area by up to 42% and reduces its delay by up to 18% compared with a conventional design.
AB - Interpolation is a technique that presumes a value between existing data, which is often used for image scaling and correction of distortion. Linear interpolation is one of the interpolation techniques which interpolates inbetween values by linearly connecting two known values. Also, bi-linear interpolation is one of interpolation techniques, which interpolates a value linearly from its four circumferences. Both of them are used practically in many cases. In this paper, we propose high-speed and small-sized linear and bi-linear interpolation circuits based on selector logics. The proposed linear and bi-linear interpolation circuits reduce carry propagation delays by using selector logics and then realize fast and small-sized circuits. We have implemented our linear interpolation circuit and bi-linear interpolation circuits in several ways and evaluated each of them. We can find out that a selector-based bi-linear interpolation circuit where its partial products are summed up by using the arithmetic operator saves its area by up to 42% and reduces its delay by up to 18% compared with a conventional design.
KW - bi-linear interpolation
KW - interpolation
KW - linear interpolation
KW - selector logics
UR - http://www.scopus.com/inward/record.url?scp=84907390850&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84907390850&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2014.6865415
DO - 10.1109/ISCAS.2014.6865415
M3 - Conference contribution
AN - SCOPUS:84907390850
SN - 9781479934324
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1436
EP - 1439
BT - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Y2 - 1 June 2014 through 5 June 2014
ER -