Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique

Kazunori Shimizu*, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder architecture based on an intermediate message-compression technique which features as follows: (i) An intermediate message compression technique enables the decoder to reduce the required memory capacity and write power dissipation, (ii) A clock gated shift register based intermediate message memory architecture enables the decoder to decompress the compressed messages in a single clock cycle while reducing the read power dissipation. The combination of the above two techniques enables the decoder to reduce the power dissipation while keeping the decoding throughput. The simulation results show that the proposed architecture improves the power efficiency up to 52% and 18% compared to that of the decoder based on the overlapped schedule and the rapid convergence schedule without the proposed techniques respectively.

Original languageEnglish
Pages (from-to)1054-1061
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number4
Publication statusPublished - 2008


  • Clock gated shift register for intermediate message
  • Intermediate
  • Low-density parity-check code
  • Message compression technique
  • Message-passing algorithm

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics


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