Low-power partial distortion sorting fast motion estimation algorithms and VLSI implementations

Yang Song*, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


This paper presents two hardware-friendly low-power oriented fast motion estimation (ME) algorithms and their VLSI implementations. The basic idea of the proposed partial distortion sorting (PDS) algorithm is to disable the search points which have larger partial distortions during the ME process, and only keep those search points with smaller ones. To further reduce the computation overhead, a simplified local PDS (LPDS) algorithm is also presented. Experiments show that the PDS and LPDS algorithms can provide almost the same image quality as full search only with 36.7 computation complexity. The proposed two algorithms can be integrated into different FSBMA architectures to save power consumption. In this paper, the 1-D inter ME architecture [12] is used as an detailed example. Under the worst working conditions (1.62 V, 125°C) and 166 MHz clock frequency, the PDS algorithm can reduce 33.3 power consumption with 4.05 K gates extra hardware cost, and the LPDS can reduce 37.8 power consumption with 1.73 K gates overhead.

Original languageEnglish
Pages (from-to)108-117
Number of pages10
JournalIEICE Transactions on Information and Systems
Issue number1
Publication statusPublished - 2007 Jan


  • Motion estimation (ME)
  • Partial distortion sorting (PDS)
  • Systolic array architecture

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence


Dive into the research topics of 'Low-power partial distortion sorting fast motion estimation algorithms and VLSI implementations'. Together they form a unique fingerprint.

Cite this