Memory array architecture and decoding scheme for 3V only sector erasable DINOR flash memory

Shi ichi Kobayashi; Hiroaki Nakat; Yuichi Kunori; Takeshi Nakayama; Yoshikazu Miyawaki; Yasushi Terada; Hiroshi Onoda; Natsuo Ajika; Masahiro Hatanaka; Hirokazu Misyoshi; Tsutomu Yoshihara

Memory array architecture and decoding scheme for 3V only sector erasable DINOR flash memory

Shi ichi Kobayashi^*, Hiroaki Nakat, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Misyoshi, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Several memory array configurations have been proposed for single power supply flash memories. This scheme realizes 1K byte sector erasure with minimized disturbance to the unselected sectors. A memory array configuration and a decoder circuits for the DINOR flash memory have been described. The hierarchical row decoder and the compact source line driver realize 1K byte sector erasure without increasing the decoder area. The decoder pitch has been relaxed to one driver per two word lines. Narrow threshold voltage distribution has been realized by the bit-by-bit programming control and the low threshold voltage detection circuit, which achieves high speed random access time t low V_cc .

Original language	English
Title of host publication	1993 Symposium on VLSI Circuits Digest of Technical Papers
Place of Publication	Piscataway, NJ, United States
Publisher	Publ by IEEE
Pages	97-98
Number of pages	2
ISBN (Print)	0780312619
Publication status	Published - 1993
Externally published	Yes
Event	1993 Symposium on VLSI Circuits Digest of Technical Papers - Kyoto, Jpn Duration: 1993 May 19 → 1993 May 21

Other

Other	1993 Symposium on VLSI Circuits Digest of Technical Papers
City	Kyoto, Jpn
Period	93/5/19 → 93/5/21

ASJC Scopus subject areas

Engineering(all)

Cite this

Kobayashi, SI, Nakat, H, Kunori, Y, Nakayama, T, Miyawaki, Y, Terada, Y, Onoda, H, Ajika, N, Hatanaka, M, Misyoshi, H & Yoshihara, T 1993, Memory array architecture and decoding scheme for 3V only sector erasable DINOR flash memory. in 1993 Symposium on VLSI Circuits Digest of Technical Papers. Publ by IEEE, Piscataway, NJ, United States, pp. 97-98, 1993 Symposium on VLSI Circuits Digest of Technical Papers, Kyoto, Jpn, 93/5/19.

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title = "Memory array architecture and decoding scheme for 3V only sector erasable DINOR flash memory",

abstract = "Several memory array configurations have been proposed for single power supply flash memories. This scheme realizes 1K byte sector erasure with minimized disturbance to the unselected sectors. A memory array configuration and a decoder circuits for the DINOR flash memory have been described. The hierarchical row decoder and the compact source line driver realize 1K byte sector erasure without increasing the decoder area. The decoder pitch has been relaxed to one driver per two word lines. Narrow threshold voltage distribution has been realized by the bit-by-bit programming control and the low threshold voltage detection circuit, which achieves high speed random access time t low Vcc .",

author = "Kobayashi, {Shi ichi} and Hiroaki Nakat and Yuichi Kunori and Takeshi Nakayama and Yoshikazu Miyawaki and Yasushi Terada and Hiroshi Onoda and Natsuo Ajika and Masahiro Hatanaka and Hirokazu Misyoshi and Tsutomu Yoshihara",

year = "1993",

language = "English",

isbn = "0780312619",

pages = "97--98",

booktitle = "1993 Symposium on VLSI Circuits Digest of Technical Papers",

publisher = "Publ by IEEE",

note = "1993 Symposium on VLSI Circuits Digest of Technical Papers ; Conference date: 19-05-1993 Through 21-05-1993",

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T1 - Memory array architecture and decoding scheme for 3V only sector erasable DINOR flash memory

AU - Kobayashi, Shi ichi

AU - Nakat, Hiroaki

AU - Kunori, Yuichi

AU - Nakayama, Takeshi

AU - Miyawaki, Yoshikazu

AU - Terada, Yasushi

AU - Onoda, Hiroshi

AU - Ajika, Natsuo

AU - Hatanaka, Masahiro

AU - Misyoshi, Hirokazu

AU - Yoshihara, Tsutomu

PY - 1993

Y1 - 1993

N2 - Several memory array configurations have been proposed for single power supply flash memories. This scheme realizes 1K byte sector erasure with minimized disturbance to the unselected sectors. A memory array configuration and a decoder circuits for the DINOR flash memory have been described. The hierarchical row decoder and the compact source line driver realize 1K byte sector erasure without increasing the decoder area. The decoder pitch has been relaxed to one driver per two word lines. Narrow threshold voltage distribution has been realized by the bit-by-bit programming control and the low threshold voltage detection circuit, which achieves high speed random access time t low Vcc .

AB - Several memory array configurations have been proposed for single power supply flash memories. This scheme realizes 1K byte sector erasure with minimized disturbance to the unselected sectors. A memory array configuration and a decoder circuits for the DINOR flash memory have been described. The hierarchical row decoder and the compact source line driver realize 1K byte sector erasure without increasing the decoder area. The decoder pitch has been relaxed to one driver per two word lines. Narrow threshold voltage distribution has been realized by the bit-by-bit programming control and the low threshold voltage detection circuit, which achieves high speed random access time t low Vcc .

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M3 - Conference contribution

AN - SCOPUS:0027843339

SN - 0780312619

SP - 97

EP - 98

BT - 1993 Symposium on VLSI Circuits Digest of Technical Papers

PB - Publ by IEEE

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T2 - 1993 Symposium on VLSI Circuits Digest of Technical Papers

Y2 - 19 May 1993 through 21 May 1993

ER -

Memory array architecture and decoding scheme for 3V only sector erasable DINOR flash memory

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ASJC Scopus subject areas

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