Memory design was carried out using one-transistor gain cell on SOI. This memory design is based on a one-transistor gain cell which is smaller, less complex to make and more scalable to sub-0.1μm generations than the existing dynamic random access memory (DRAM) cells, without resorting to new materials and device structure. Transient analysis of a device simulation was also discussed to verify operation of the floating body transistor cell (FBC).
|Digest of Technical Papers - IEEE International Solid-State Circuits Conference
|Published - 2002 Jan 1
|2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States
Duration: 2002 Feb 3 → 2002 Feb 7
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering