Memory design using one-transistor gain cell on SOI

Takashi Ohsawa; Katsuyuki Fujita; Tomoki Higashi; Yoshihisa Iwata; Takeshi Kajiyama; Yoshiaki Asao; Kazumasa Sunouchi

Memory design using one-transistor gain cell on SOI

Takashi Ohsawa^*, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

2 Citations (Scopus)

Abstract

A 512 kb DRAM has a 7F² one-transistor gain cell (F=0.18 μm) on SOI. The array driving method makes selective write possible. Basic operation is verified by device simulation and hardware measurement. Simulations show 40 ns access time. Non-destructive readout and Cb/Cs-free signal development improve cell efficiency.

Original language	English
Pages (from-to)	114-115+425
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Issue number	SUPPL.
Publication status	Published - 2002 Jan 1
Externally published	Yes
Event	2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States Duration: 2002 Feb 3 → 2002 Feb 7

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "Memory design using one-transistor gain cell on SOI",

abstract = "A 512 kb DRAM has a 7F2 one-transistor gain cell (F=0.18 μm) on SOI. The array driving method makes selective write possible. Basic operation is verified by device simulation and hardware measurement. Simulations show 40 ns access time. Non-destructive readout and Cb/Cs-free signal development improve cell efficiency.",

author = "Takashi Ohsawa and Katsuyuki Fujita and Tomoki Higashi and Yoshihisa Iwata and Takeshi Kajiyama and Yoshiaki Asao and Kazumasa Sunouchi",

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journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

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note = "2002 IEEE International Solid-State Circuits Conference ; Conference date: 03-02-2002 Through 07-02-2002",

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T1 - Memory design using one-transistor gain cell on SOI

AU - Ohsawa, Takashi

AU - Fujita, Katsuyuki

AU - Higashi, Tomoki

AU - Iwata, Yoshihisa

AU - Kajiyama, Takeshi

AU - Asao, Yoshiaki

AU - Sunouchi, Kazumasa

PY - 2002/1/1

Y1 - 2002/1/1

N2 - A 512 kb DRAM has a 7F2 one-transistor gain cell (F=0.18 μm) on SOI. The array driving method makes selective write possible. Basic operation is verified by device simulation and hardware measurement. Simulations show 40 ns access time. Non-destructive readout and Cb/Cs-free signal development improve cell efficiency.

AB - A 512 kb DRAM has a 7F2 one-transistor gain cell (F=0.18 μm) on SOI. The array driving method makes selective write possible. Basic operation is verified by device simulation and hardware measurement. Simulations show 40 ns access time. Non-destructive readout and Cb/Cs-free signal development improve cell efficiency.

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M3 - Conference article

AN - SCOPUS:0036224159

SN - 0193-6530

SP - 114-115+425

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

IS - SUPPL.

T2 - 2002 IEEE International Solid-State Circuits Conference

Y2 - 3 February 2002 through 7 February 2002

ER -

Memory design using one-transistor gain cell on SOI

Abstract

ASJC Scopus subject areas

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