Method for acceleration of logic simulations

Masayoshi Sakakura*, Yoshiaki Fukazawa

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

1 Citation (Scopus)


We present a method for acceleration of logic simulations. The logic simulation is mainly used to detect malfunctions in the logical design phase. As the size of logical circuits grows, acceleration of the logic simulation becomes increasingly required. Several acceleration methods have been presented for this purpose. The outstanding feature of our method is that it accelerates the simulation speed in accordance with the dynamic behaviours of target circuits. A global dynamic behaviour is predicted to realize this feature, through the investigation of the relationship among gates in the early stage of the simulation. Using the relationships, a logic simulation is accelerated by a process called 'grouping'. We have confirmed that the dynamic information of the circuits accelerates logical simulation by the evaluation system.

Original languageEnglish
Number of pages4
Publication statusPublished - 1995 Jan 1
EventProceedings of the 1994 IEEE Region 10's 9th Annual International Conference (TENCON'94). Part 1 (of 2) - Singapore, Singapore
Duration: 1994 Aug 221994 Aug 26


OtherProceedings of the 1994 IEEE Region 10's 9th Annual International Conference (TENCON'94). Part 1 (of 2)
CitySingapore, Singapore

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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