TY - GEN
T1 - MeV-BORON IMPLANTED BURIED BARRIER FOR SOFT ERROR REDUCTION IN MEGABIT DRAM.
AU - Matsuda, Y.
AU - Tsukamoto, K.
AU - Inuishi, M.
AU - Shimizu, M.
AU - Asakura, M.
AU - Fujishima, K.
AU - Komori, J.
AU - Akasaka, Y.
PY - 1987
Y1 - 1987
N2 - The soft error rate (SER) reduction by an MeV-boron implanted buried barrier is presented in applying a 1Mbit NMOS DRAM. Improvement by a factor of more than X100 was obtained in the bit line mode SER and also by a factor of X50 in the cell mode SER compared with the HiC structure. With the aid of the buried barrier, less than 100 FIT of the SER would be achieved in megabit DRAM with the storage capacitance of 24fF at 5V operation.
AB - The soft error rate (SER) reduction by an MeV-boron implanted buried barrier is presented in applying a 1Mbit NMOS DRAM. Improvement by a factor of more than X100 was obtained in the bit line mode SER and also by a factor of X50 in the cell mode SER compared with the HiC structure. With the aid of the buried barrier, less than 100 FIT of the SER would be achieved in megabit DRAM with the storage capacitance of 24fF at 5V operation.
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U2 - 10.7567/ssdm.1987.a-1-4
DO - 10.7567/ssdm.1987.a-1-4
M3 - Conference contribution
AN - SCOPUS:0023586227
SN - 4930813212
SN - 9784930813213
T3 - Conference on Solid State Devices and Materials
SP - 23
EP - 26
BT - Conference on Solid State Devices and Materials
PB - Japan Soc of Applied Physics
ER -