Abstract
In the hardware synthesis from high-level language such as C, bit length of variables is one of the key issues on the area and speed optimization. Usually, designers are required to specify the word length of each variable manually, and verify the correctness by the simulation on huge data. In this paper, we propose an optimization method of fractional wold length of floating-point variables in the floating to fixed-point conversion of variables. The amount of round-off errors are formulated with parameters and propagated via data flow graphs. The non-linear programming is used to solve the fractional wordlength minimization problem. The method does not require the simulation on huge data, and is very fast compared to ones based on the simulation. We have shown the effect on several programs.
| Original language | English |
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| Pages | 80-85 |
| Number of pages | 6 |
| Publication status | Published - 2004 Jun 1 |
| Event | Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan Duration: 2004 Jan 27 → 2004 Jan 30 |
Conference
| Conference | Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 |
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| Country/Territory | Japan |
| City | Yokohama |
| Period | 04/1/27 → 04/1/30 |
ASJC Scopus subject areas
- Computer Science Applications
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering