Minimum skew and minimum path length routing in VLSI layout design

Masato Edahiro*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingChapter

11 Citations (Scopus)


This paper presents a routing algorithm to accomplish the minimum skew as well as the minimum path length. For a net, this algorithm guarantees an equidistant routing for all the paths from the fan-out terminal to fan-in terminals of the net. In addition, the minimum path length routing is achieved for these paths among all the minimum skew routings. Since this algorithm allows each terminal to have a weight as a load, the skew for a net is still minimized even if terminals in the net have different loads. Moreover, a bottom-up routing method is proposed for circuits with a hierarchy. In this method, nets are routed first at the bottom of the logic hierarchy, and then routings are performed in higher levels of the hierarchy taking routing lengths in the lower levels into account. Owing to the bottom-up routing method, the proposed algorithm also guarantees skew minimization for circuits with a hierarchy.

Original languageEnglish
Title of host publicationNEC Research and Development
PublisherPubl by Nippon Electric Co
Number of pages7
Publication statusPublished - 1991 Oct
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'Minimum skew and minimum path length routing in VLSI layout design'. Together they form a unique fingerprint.

Cite this