Mixed bus width architecture for low cost AES VLSI design

Yibo Fan; Jidong Wang; Takeshi Ikenaga; Satoshi Goto

doi:10.1109/ICASIC.2007.4415765

Mixed bus width architecture for low cost AES VLSI design

Yibo Fan^*, Jidong Wang, Takeshi Ikenaga, Satoshi Goto

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

With the increase of security problem, AES is widely used in a lot of secure systems. For some low data throughput applications, low cost design is more attractive than high speed design. In this paper, low cost hardware architecture for AES algorithm is proposed. Mixed bus width architecture is used to reduce hardware cost and shorten critical path. The experimental results show that the lowest hardware cost implementation of AES algorithm is 4678 Gates. The corresponding frequency is 80MHz and the throughput is 51Mbps. This architecture is very suitable for mid-throughput, low power and low hardware cost systems such as mobile system.

Original language	English
Title of host publication	ASICON 2007 - 2007 7th International Conference on ASIC Proceeding
Pages	854-857
Number of pages	4
DOIs	https://doi.org/10.1109/ICASIC.2007.4415765
Publication status	Published - 2007 Dec 1
Event	2007 7th International Conference on ASIC, ASICON 2007 - Guilin, China Duration: 2007 Oct 26 → 2007 Oct 29

Publication series

Name	ASICON 2007 - 2007 7th International Conference on ASIC Proceeding

Conference

Conference	2007 7th International Conference on ASIC, ASICON 2007
Country/Territory	China
City	Guilin
Period	07/10/26 → 07/10/29

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ICASIC.2007.4415765

Cite this

Fan, Y, Wang, J, Ikenaga, T & Goto, S 2007, Mixed bus width architecture for low cost AES VLSI design. in ASICON 2007 - 2007 7th International Conference on ASIC Proceeding., 4415765, ASICON 2007 - 2007 7th International Conference on ASIC Proceeding, pp. 854-857, 2007 7th International Conference on ASIC, ASICON 2007, Guilin, China, 07/10/26. https://doi.org/10.1109/ICASIC.2007.4415765

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Mixed bus width architecture for low cost AES VLSI design

Abstract

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