Modeling the impact of input-to-output coupling capacitance on power dissipation estimation in deep submicron CMOS circuits

Huang Zhangcai; Li Na; Huang Sui; Yasuaki Inoue

Modeling the impact of input-to-output coupling capacitance on power dissipation estimation in deep submicron CMOS circuits

Huang Zhangcai^*, Li Na, Huang Sui, Yasuaki Inoue

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper modeling the impact of input-to-output coupling capacitance on power dissipation estimation in submicron CMOS circuits is proposed. Compared with conventional methods, the proposed model is much accurate because it considers the impact of the input-to-output capacitance on power dissipation estimation. In addition, the proposed model can estimate the impact of coupling capacitance on serial gates. The experimental results show that the proposed model can obtain an considerable improvement in accuracy.

Original language	English
Title of host publication	ICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007
Pages	1154-1157
Number of pages	4
Publication status	Published - 2008
Event	ICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007 - Kokura Duration: 2007 Jul 11 → 2007 Jul 13

Other

Other	ICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007
City	Kokura
Period	07/7/11 → 07/7/13

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

Modeling the impact of input-to-output coupling capacitance on power dissipation estimation in deep submicron CMOS circuits. / Zhangcai, Huang; Na, Li; Sui, Huang et al.

ICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007. 2008. p. 1154-1157 4348251.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhangcai, H, Na, L, Sui, H & Inoue, Y 2008, Modeling the impact of input-to-output coupling capacitance on power dissipation estimation in deep submicron CMOS circuits. in ICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007., 4348251, pp. 1154-1157, ICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007, Kokura, 07/7/11.

@inproceedings{94969cea9c3e4f79a9ab30dab7ac7496,

title = "Modeling the impact of input-to-output coupling capacitance on power dissipation estimation in deep submicron CMOS circuits",

abstract = "In this paper modeling the impact of input-to-output coupling capacitance on power dissipation estimation in submicron CMOS circuits is proposed. Compared with conventional methods, the proposed model is much accurate because it considers the impact of the input-to-output capacitance on power dissipation estimation. In addition, the proposed model can estimate the impact of coupling capacitance on serial gates. The experimental results show that the proposed model can obtain an considerable improvement in accuracy.",

author = "Huang Zhangcai and Li Na and Huang Sui and Yasuaki Inoue",

year = "2008",

language = "English",

isbn = "9781424414741",

pages = "1154--1157",

booktitle = "ICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007",

note = "ICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007 ; Conference date: 11-07-2007 Through 13-07-2007",

}

TY - GEN

T1 - Modeling the impact of input-to-output coupling capacitance on power dissipation estimation in deep submicron CMOS circuits

AU - Zhangcai, Huang

AU - Na, Li

AU - Sui, Huang

AU - Inoue, Yasuaki

PY - 2008

Y1 - 2008

N2 - In this paper modeling the impact of input-to-output coupling capacitance on power dissipation estimation in submicron CMOS circuits is proposed. Compared with conventional methods, the proposed model is much accurate because it considers the impact of the input-to-output capacitance on power dissipation estimation. In addition, the proposed model can estimate the impact of coupling capacitance on serial gates. The experimental results show that the proposed model can obtain an considerable improvement in accuracy.

AB - In this paper modeling the impact of input-to-output coupling capacitance on power dissipation estimation in submicron CMOS circuits is proposed. Compared with conventional methods, the proposed model is much accurate because it considers the impact of the input-to-output capacitance on power dissipation estimation. In addition, the proposed model can estimate the impact of coupling capacitance on serial gates. The experimental results show that the proposed model can obtain an considerable improvement in accuracy.

UR - http://www.scopus.com/inward/record.url?scp=40649129552&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=40649129552&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:40649129552

SN - 9781424414741

SP - 1154

EP - 1157

BT - ICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007

T2 - ICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007

Y2 - 11 July 2007 through 13 July 2007

ER -

Modeling the impact of input-to-output coupling capacitance on power dissipation estimation in deep submicron CMOS circuits

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