Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies

Zhangcai Huang*, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    43 Citations (Scopus)


    With the scaling of complementary metal-oxide-semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.

    Original languageEnglish
    Article number5395729
    Pages (from-to)250-260
    Number of pages11
    JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    Issue number2
    Publication statusPublished - 2010 Feb


    • CMOS inverter
    • Gate delay
    • Nanometer technology
    • Overshooting time
    • Switch-resistor model
    • Timing analysis

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Software


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