Modeling the overshooting effect for CMOS inverter in nanometer technologies

Huang Zhangcai; Yu Hong; Atsushi Kurokawa; Yasuaki Inoue

doi:10.1109/ASPDAC.2007.358046

Modeling the overshooting effect for CMOS inverter in nanometer technologies

Huang Zhangcai^*, Yu Hong, Atsushi Kurokawa, Yasuaki Inoue

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

With the scaling of CMOS technology, the over-shooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer technologies. Furthermore, the influence of process variation on the overshooting time is illustrated based on the proposed model. And the accuracy of the proposed model is proved to greatly agree with SPICE simulation results.

Original language	English
Title of host publication	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages	565-570
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2007.358046
Publication status	Published - 2007
Event	ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama Duration: 2007 Jan 23 → 2007 Jan 27

Other

Other	ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
City	Yokohama
Period	07/1/23 → 07/1/27

ASJC Scopus subject areas

Engineering(all)

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10.1109/ASPDAC.2007.358046

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Zhangcai, H, Hong, Y, Kurokawa, A & Inoue, Y 2007, Modeling the overshooting effect for CMOS inverter in nanometer technologies. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC., 4196092, pp. 565-570, ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007, Yokohama, 07/1/23. https://doi.org/10.1109/ASPDAC.2007.358046

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abstract = "With the scaling of CMOS technology, the over-shooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer technologies. Furthermore, the influence of process variation on the overshooting time is illustrated based on the proposed model. And the accuracy of the proposed model is proved to greatly agree with SPICE simulation results.",

author = "Huang Zhangcai and Yu Hong and Atsushi Kurokawa and Yasuaki Inoue",

year = "2007",

doi = "10.1109/ASPDAC.2007.358046",

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AU - Kurokawa, Atsushi

AU - Inoue, Yasuaki

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N2 - With the scaling of CMOS technology, the over-shooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer technologies. Furthermore, the influence of process variation on the overshooting time is illustrated based on the proposed model. And the accuracy of the proposed model is proved to greatly agree with SPICE simulation results.

AB - With the scaling of CMOS technology, the over-shooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer technologies. Furthermore, the influence of process variation on the overshooting time is illustrated based on the proposed model. And the accuracy of the proposed model is proved to greatly agree with SPICE simulation results.

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BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

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ER -

Modeling the overshooting effect for CMOS inverter in nanometer technologies

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