Modeling the overshooting effect in the submicron CMOS inverters

Zhangcai Huang; Atsushi Kurokawa; Yasuaki Inoue

Modeling the overshooting effect in the submicron CMOS inverters

Zhangcai Huang^*, Atsushi Kurokawa, Yasuaki Inoue

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

Original language	English
Title of host publication	2005 International Conference on Communications, Circuits and Systems - Proceedings
Pages	1191-1195
Number of pages	5
Volume	2
Publication status	Published - 2005
Externally published	Yes
Event	2005 International Conference on Communications, Circuits and Systems - Hong Kong Duration: 2005 May 27 → 2005 May 30

Other

Other	2005 International Conference on Communications, Circuits and Systems
City	Hong Kong
Period	05/5/27 → 05/5/30

ASJC Scopus subject areas

Engineering(all)

Cite this

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title = "Modeling the overshooting effect in the submicron CMOS inverters",

abstract = "The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.",

author = "Zhangcai Huang and Atsushi Kurokawa and Yasuaki Inoue",

year = "2005",

language = "English",

isbn = "0780390156",

volume = "2",

pages = "1191--1195",

booktitle = "2005 International Conference on Communications, Circuits and Systems - Proceedings",

note = "2005 International Conference on Communications, Circuits and Systems ; Conference date: 27-05-2005 Through 30-05-2005",

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T1 - Modeling the overshooting effect in the submicron CMOS inverters

AU - Huang, Zhangcai

AU - Kurokawa, Atsushi

AU - Inoue, Yasuaki

PY - 2005

Y1 - 2005

N2 - The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

AB - The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

UR - http://www.scopus.com/inward/record.url?scp=29844454521&partnerID=8YFLogxK

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M3 - Conference contribution

AN - SCOPUS:29844454521

SN - 0780390156

VL - 2

SP - 1191

EP - 1195

BT - 2005 International Conference on Communications, Circuits and Systems - Proceedings

T2 - 2005 International Conference on Communications, Circuits and Systems

Y2 - 27 May 2005 through 30 May 2005

ER -

Modeling the overshooting effect in the submicron CMOS inverters

Abstract

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ASJC Scopus subject areas

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