Modeling the overshooting effect of multi-input gate in nanometer technologies

Li Ding; Zhangcai Huang; Minglu Jiang; Atsushi Kurokawa; Yasuaki Inoue

doi:10.1109/MWSCAS.2011.6026587

Modeling the overshooting effect of multi-input gate in nanometer technologies

Li Ding^*, Zhangcai Huang, Minglu Jiang, Atsushi Kurokawa, Yasuaki Inoue

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

With the advent of nanometer age in digital circuits, the overshooting time becomes a dominating component of gate delay for CMOS logic gates. Till now, few researches have focused on the overshooting effect of multi-input gate. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.

Original language	English
Title of host publication	Midwest Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/MWSCAS.2011.6026587
Publication status	Published - 2011
Event	54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul Duration: 2011 Aug 7 → 2011 Aug 10

Other

Other	54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
City	Seoul
Period	11/8/7 → 11/8/10

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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10.1109/MWSCAS.2011.6026587

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title = "Modeling the overshooting effect of multi-input gate in nanometer technologies",

abstract = "With the advent of nanometer age in digital circuits, the overshooting time becomes a dominating component of gate delay for CMOS logic gates. Till now, few researches have focused on the overshooting effect of multi-input gate. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.",

author = "Li Ding and Zhangcai Huang and Minglu Jiang and Atsushi Kurokawa and Yasuaki Inoue",

year = "2011",

doi = "10.1109/MWSCAS.2011.6026587",

language = "English",

isbn = "9781612848570",

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note = "54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 ; Conference date: 07-08-2011 Through 10-08-2011",

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AU - Ding, Li

AU - Huang, Zhangcai

AU - Jiang, Minglu

AU - Kurokawa, Atsushi

AU - Inoue, Yasuaki

PY - 2011

Y1 - 2011

N2 - With the advent of nanometer age in digital circuits, the overshooting time becomes a dominating component of gate delay for CMOS logic gates. Till now, few researches have focused on the overshooting effect of multi-input gate. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.

AB - With the advent of nanometer age in digital circuits, the overshooting time becomes a dominating component of gate delay for CMOS logic gates. Till now, few researches have focused on the overshooting effect of multi-input gate. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.

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U2 - 10.1109/MWSCAS.2011.6026587

DO - 10.1109/MWSCAS.2011.6026587

M3 - Conference contribution

AN - SCOPUS:80053636821

SN - 9781612848570

BT - Midwest Symposium on Circuits and Systems

T2 - 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011

Y2 - 7 August 2011 through 10 August 2011

ER -

Modeling the overshooting effect of multi-input gate in nanometer technologies

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